>>>>> "GL" == Grant Likely <[EMAIL PROTECTED]> writes:
Hi,
GL> Currently virtex support in mainline make use of the
GL> infrastructure in arch/ppc/syslib/ppc_sys.c for registering common
GL> devices on virtex ppc405 platforms. The ppc_sys.c code is not
GL> well suited to the dynamic nature of FPGA designs and makes adding
GL> new board ports more complex. This patch adds a new listing of
GL> common devices which does not depend on the ppc_sys.c
GL> infrastructure.
GL> +/* UART 8250 driver platform data table */
GL> +struct plat_serial8250_port virtex_serial_platform_data[] = {
GL> +#if defined(XPAR_UARTNS550_0_BASEADDR)
GL> + XPAR_UART(0),
GL> +#endif
GL> +#if defined(XPAR_UARTNS550_1_BASEADDR)
GL> + XPAR_UART(1),
GL> +#endif
GL> +#if defined(XPAR_UARTNS550_2_BASEADDR)
GL> + XPAR_UART(2),
GL> +#endif
GL> +#if defined(XPAR_UARTNS550_3_BASEADDR)
GL> + XPAR_UART(3),
GL> +#endif
GL> + { }, /* terminated by empty record */
GL> +};
Could we at the same time increase the amount of UARTs supported? We
have designs with 5 16550s.
Other than that,
Acked-by: Peter Korsgaard <[EMAIL PROTECTED]>
--
Bye, Peter Korsgaard
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