Hi Andy,
> >
> > Is any given board going to have at runtime (i.e. not jumper
> > selectable) both a phy and a tbi (I'm not very familiar with the
> > latter, so I apologize if this is a dumb question). If not, I'd
> > stick with phy-handle and have something in the phy node to
> > indicate that it's tbi.
>
>
> Yes. That will be the more common case. The TBI PHYs are connected
> to the MDIO pins of each TSEC. The TBIPA register defines what
> address it sits on. It is used to configure non MII-style data
> connections, usually to another PHY. For instance, to configure a
> TSEC for SGMII, you first configure the attached TBI to communicate
> with the on-chip SERDES.
>
> While the TBI devices technically all sit on MDIO busses, only the
> TBI PHY connected to the first TSEC will interfere with MDIO
> transactions. I don't think we need to create nodes for each of the
> TBIs. They exist as a secondary part of the ethernet controller, and
> their address is only really important to that controller.
>
> I still think it should just be a property of the ethernet node. We
> aren't describing the TBI, we're describing a setting for the
> ethernet controller's register.
>
Like this? Do we need to have one for each [EMAIL PROTECTED]
[EMAIL PROTECTED] {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <24000 1000>;
mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1f>;
tbi-address = <0x1e>;
};
Joe
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