Hi Mike, 
In my application the time I get with MAC timestamping is good enough, but not 
the 1PPS signal. With two boards, one master and one slave connected 
back-to-back the max 1PPS jitter is approximately 200ns.
The 1PPS on the slave side will be used to regenerate a higher frequency clock. 
 My goal is to get down to 10-20ns 1PPS jitter.
I am using a high stability external PTP clock reference for both master and 
slave.
BR
AD


> Sent: Monday, January 21, 2019 at 2:15 PM
> From: "Lynch, Mike" <mike.ly...@hbm.com>
> To: "Arthur Dent" <arthurd...@cyberdude.com>
> Subject: RE: [Linuxptp-users] PHYs supporting HW timestamping
>
> Are you using an internal or external PTP reference clock?  Is 150Mhz 
> accurate enough or do you need to account for the latency between the PHY and 
> the MAC?
> 
> -----Original Message-----
> From: Arthur Dent [mailto:arthurd...@cyberdude.com] 
> Sent: Monday, January 21, 2019 3:08 AM
> To: linuxptp-users@lists.sourceforge.net
> Subject: [Linuxptp-users] PHYs supporting HW timestamping
> 
> Hi
> On my Cyclone V SoC board I have ptp running with HW timestamping in MAC 
> (stmmac), but I need even better accuracy, i.e. hardware timestamping in PHY. 
> Is my only option to use TI’s DP83640 PHY (which only supports 100Mb) or am I 
> reading the information on 
> http://atpscan.global.hornetsecurity.com/index.php?atp_str=6oEZ_WXDKGAgauHn9VB73M-nT30yjx2ABcTlxmWMq6JKzSTQ7blQiVqL8avnNdU4IWMtn73mMShRf4sHOZqJ6G-pQlFVkhKaFMUjHFrGN09wLO54ty3kciK4oEzA0W-w1SsmHGzsH5Nca8_FAfL1Nx_SkGUUcbRWDpyrFhWgL6dCnPZd7_6L-eTBZq7UAQ6L_sRne2KmnqLsv_IyDHhODWoIF-8xU0sb9YHQJZYt2LeAeHV3Q8M4nCTf78tJhMxhlZBtFZoe5vvEWDJTz73IhqXgT97gaScEyTICQYC7IVBrXammN_QlBPIq2iM6OiM5MjZmM2JjMGMzYWMjOjojCy5R8n1LNQf7w6MmG4hPhA
>  0incorrectly?
> BR
> AD
> 
> 
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