Hi Wolfgang, thanks for the information. Very useful mii-tool! Well I have now interfaced the DP83640 evaluation board to my Cyclone V SoC (needed to write a MII-RMII adapter), and has Ethernet traffic up an running through the DP83640. A bit slow, probably some FIFO issues but no errors.
Enabled the kernel flags: CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NATIONAL_PHY=y in addition to the PTP/1588 configs that was set when using timestamp in MAC. But, I have some PTP issues: phc_ctl seems to report correctly: phc_ctl /dev/ptp0 freq 10000 set 0.0 wait 10.0 get phc_ctl[18.251]: adjusted clock frequency offset to 10000.000000ppb phc_ctl[18.252]: set clock time to 0.000000000 or Thu Jan 1 01:00:00 1970 phc_ctl[28.253]: process slept for 10.000000 seconds phc_ctl[28.253]: clock time is 10.000473795 or Thu Jan 1 01:00:10 1970 but not ptp4l: ptp4l -m -s -q -i eth0 -p /dev/ptp0 -f /etc/ptp4lhw.conf ptp4l[44.689]: selected /dev/ptp0 as PTP clock ptp4l[44.695]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[44.695]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[46.603]: port 1: new foreign master f2a466.fffe.8ee535-1 ptp4l[50.604]: selected best master clock f2a466.fffe.8ee535 ptp4l[50.604]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[52.602]: master offset 126506903468910 s0 freq -10000 path delay 10460 ptp4l[53.602]: master offset 126506903468840 s1 freq -10070 path delay 10490 ptp4l[54.602]: master offset 126506903468440 s2 freq +1953124 path delay 10490 ptp4l[54.602]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[55.602]: master offset 126506903468840 s2 freq +1953124 path delay 10490 ptp4l[56.602]: master offset 126506903468570 s2 freq +1953124 path delay 10520 ptp4l[57.602]: master offset 126506903468640 s2 freq +1953124 path delay 10570 ... and so on. I think the freq +1953124 is at its max value. I addition to /dev/ptp0 I also have/dev/ptp1 (for the MAC). Can this confuse the system? I read somewhere that the MACs PHC must be disabled...? ll /sys/class/ptp/ lrwxrwxrwx 1 root root 0 Jan 1 1970 ptp0 -> ../../devices/platform/soc/ff700000.ethernet/stmmac-1:00/ptp/ptp0 lrwxrwxrwx 1 root root 0 Jan 24 15:06 ptp1 -> ../../devices/platform/soc/ff700000.ethernet/ptp/ptp1 If anyone can point me in the right direction it would be greatly appreciated. BR AD Sent: Wednesday, January 23, 2019 at 6:02 PM From: "Wolfgang Hennig" <when...@xia.com> To: "Arthur Dent" <arthurd...@cyberdude.com> Cc: linuxptp-users@lists.sourceforge.net Subject: Re: [Linuxptp-users] PHYs supporting HW timestamping I went through this some time ago with a Zynq SoC (MicroZed board). Attached is a summary of the steps I took, perhaps some of it also applies to your board. To generate the PPS signal from the DP83640 GPIO you would need to configure its internal registers. I found one can do that either in the Kernel driver dp83640.c (fixed setup) or with mii-tool (more interactively). My customized version of mii-tool is available at http://support.xia.com/default.asp?W772 Wolfgang On 1/23/2019 4:47 AM, Arthur Dent wrote: > Hi, thanks for the information on alternative 1 Gb PHYs (VSC8572 and LAN7430). > A DP83640 evaluation board arrived today so I have decided to start out with > that to see what kind of 1PPS accuracy I can get, and later decide if a 1 Gb > interface is actually required for my application. > BR > AD > > > Sent: Tuesday, January 22, 2019 at 12:26 AM > From: "David Mirabito"<davi...@arista.com> > To: "Arthur Dent"<arthurd...@cyberdude.com> > Cc: linuxptp-users@lists.sourceforge.net > Subject: Re: [Linuxptp-users] PHYs supporting HW timestamping > > It's not on the list (probably due to not being ptp-ready "out of the box" > under Linux) but Microsemi's VSC8572 (nee Vitesse) and family could do the > job (for 2-step PTP). > https://www.microsemi.com/product-directory/gigabit-ethernet-phys/3905-vsc8572[https://www.microsemi.com/product-directory/gigabit-ethernet-phys/3905-vsc8572] > > > For various reasons we ended up not using this feature so unfortunately I > can't comment on the effort required to make it happen. > Whilst there seems to be a Linux phylib driver for the part, last I checked > timestamping wasn't implemented so there could be some fair bringup work. > > YMMV, but the part exists and hopefully is a useful datapoint in your search. > > - David > > On Mon, 21 Jan 2019 at 20:08, Arthur > Dent<arthurd...@cyberdude.com[mailto:arthurd...@cyberdude.com]> wrote:Hi > On my Cyclone V SoC board I have ptp running with HW timestamping in MAC > (stmmac), but I need even better accuracy, i.e. hardware timestamping in PHY. > Is my only option to use TI’s DP83640 PHY (which only supports 100Mb) or am I > reading the information on > http://linuxptp.sourceforge.net[http://linuxptp.sourceforge.net][http://linuxptp.sourceforge.net[http://linuxptp.sourceforge.net]] > 0incorrectly? > BR > AD > > > _______________________________________________ > Linuxptp-users mailing list > Linuxptp-users@lists.sourceforge.net[mailto:Linuxptp-users@lists.sourceforge.net] > https://lists.sourceforge.net/lists/listinfo/linuxptp-users[https://lists.sourceforge.net/lists/listinfo/linuxptp-users] > > > _______________________________________________ > Linuxptp-users mailing list > Linuxptp-users@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/linuxptp-users[https://lists.sourceforge.net/lists/listinfo/linuxptp-users] -- Wolfgang Hennig, Ph.D. XIA LLC 31057 Genstar Rd. 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