================ @@ -188,6 +190,35 @@ void DivergenceLoweringHelper::constrainAsLaneMask(Incoming &In) { In.Reg = Copy.getReg(0); } +void replaceUsesOfRegInInstWith(Register Reg, MachineInstr *Inst, + Register NewReg) { + for (MachineOperand &Op : Inst->operands()) { + if (Op.isReg() && Op.getReg() == Reg) + Op.setReg(NewReg); + } +} + +bool DivergenceLoweringHelper::lowerTemporalDivergence() { + AMDGPU::IntrinsicLaneMaskAnalyzer ILMA(*MF); + + for (auto [Inst, UseInst, _] : MUI->getTemporalDivergenceList()) { + Register Reg = Inst->getOperand(0).getReg(); + if (MRI->getType(Reg) == LLT::scalar(1) || MUI->isDivergent(Reg) || + ILMA.isS32S64LaneMask(Reg)) + continue; + + MachineBasicBlock *MBB = Inst->getParent(); + B.setInsertPt(*MBB, MBB->SkipPHIsAndLabels(std::next(Inst->getIterator()))); + + Register VgprReg = MRI->createGenericVirtualRegister(MRI->getType(Reg)); ---------------- petar-avramovic wrote:
It unnecessarily complicates new Reg bank select, regbankselect will set vgpr there. Also copy has implicit exec, should be special enough to indicate what we are doing. https://github.com/llvm/llvm-project/pull/124298 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits