================
@@ -131,6 +131,40 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI.getOperand(1).getReg();
+ unsigned Opc = MI.getOpcode();
+ if (Ty == S32 || Ty == S16) {
+ auto True = B.buildConstant({VgprRB, Ty}, Opc == G_SEXT ? -1 : 1);
+ auto False = B.buildConstant({VgprRB, Ty}, 0);
+ B.buildSelect(Dst, Src, True, False);
+ }
+ if (Ty == S64) {
----------------
Pierre-vh wrote:
```suggestion
} else if (Ty == S64) {
```
Can also add a final `else` with `llvm_unreachable`
https://github.com/llvm/llvm-project/pull/132383
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
