================
@@ -292,13 +311,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
case Ext32To64: {
const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg());
MachineInstrBuilder Hi;
-
- if (MI.getOpcode() == AMDGPU::G_ZEXT) {
+ switch (MI.getOpcode()) {
+ case AMDGPU::G_ZEXT: {
Hi = B.buildConstant({RB, S32}, 0);
- } else {
+ break;
+ }
+ case AMDGPU::G_SEXT: {
// Replicate sign bit from 32-bit extended part.
auto ShiftAmt = B.buildConstant({RB, S32}, 31);
Hi = B.buildAShr({RB, S32}, MI.getOperand(1).getReg(), ShiftAmt);
+ break;
+ }
+ case AMDGPU::G_ANYEXT: {
+ Hi = B.buildUndef({RB, S32});
----------------
arsenm wrote:
poison, but not sure the poison PR got merged yet
https://github.com/llvm/llvm-project/pull/132383
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