https://github.com/JoshdRod created https://github.com/llvm/llvm-project/pull/171448
sli intrinsic now lowers correctly for all vector types. >From 2045520c433183c633ff5ea84e8708b8a37cec51 Mon Sep 17 00:00:00 2001 From: Josh Rodriguez <[email protected]> Date: Tue, 9 Dec 2025 14:27:56 +0000 Subject: [PATCH] [GlobalISel][AArch64] Added support for sli intrinsic sli intrinsic now lowers correctly for all vector types. --- llvm/lib/Target/AArch64/AArch64InstrGISel.td | 7 +++++++ llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 7 ++++++- .../Target/AArch64/GISel/AArch64RegisterBankInfo.cpp | 2 ++ llvm/test/CodeGen/AArch64/arm64-vshift.ll | 10 ---------- 4 files changed, 15 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td index 75354e4098fb4..3002547eb2d79 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td +++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td @@ -270,6 +270,12 @@ def G_URSHR: AArch64GenericInstruction { let hasSideEffects = 0; } +def G_VSLI: AArch64GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3); + let hasSideEffects = 0; +} + // Generic instruction for the BSP pseudo. It is expanded into BSP, which // expands into BSL/BIT/BIF after register allocation. def G_BSP : AArch64GenericInstruction { @@ -321,6 +327,7 @@ def : GINodeEquiv<G_USDOT, AArch64usdot>; def : GINodeEquiv<G_SQSHLU, AArch64sqshlui>; def : GINodeEquiv<G_SRSHR, AArch64srshri>; def : GINodeEquiv<G_URSHR, AArch64urshri>; +def : GINodeEquiv<G_VSLI, AArch64vsli>; def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>; diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index 8951ccfbd3352..02f1c5a7be4b2 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -1949,6 +1949,11 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, return false; } } + case Intrinsic::aarch64_neon_vsli: { + MIB.buildInstr(AArch64::G_VSLI, {MI.getOperand(0)}, {MI.getOperand(2), MI.getOperand(3), MI.getOperand(4).getImm()}); + MI.eraseFromParent(); + break; + } case Intrinsic::aarch64_neon_abs: { // Lower the intrinsic to G_ABS. MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)}); @@ -2598,4 +2603,4 @@ bool AArch64LegalizerInfo::legalizeFptrunc(MachineInstr &MI, MRI.replaceRegWith(Dst, Fin); MI.eraseFromParent(); return true; -} \ No newline at end of file +} diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp index 84bc3f1e14a7a..8cd7c73f157e3 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp @@ -575,6 +575,7 @@ bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI, case TargetOpcode::G_LROUND: case TargetOpcode::G_LLROUND: case AArch64::G_PMULL: + case AArch64::G_VSLI: return true; case TargetOpcode::G_INTRINSIC: switch (cast<GIntrinsic>(MI).getIntrinsicID()) { @@ -613,6 +614,7 @@ bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI, case TargetOpcode::G_INSERT_VECTOR_ELT: case TargetOpcode::G_BUILD_VECTOR: case TargetOpcode::G_BUILD_VECTOR_TRUNC: + case AArch64::G_VSLI: return true; case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: switch (cast<GIntrinsic>(MI).getIntrinsicID()) { diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll index a316a4bc543b5..05ddb4b5a7c64 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll @@ -2,16 +2,6 @@ ; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD ; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI -; CHECK-GI: warning: Instruction selection used fallback path for sli8b -; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli4h -; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli2s -; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli1d -; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli1d_imm0 -; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli16b -; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli8h -; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli4s -; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli2d - define <8 x i8> @sqshl8b(ptr %A, ptr %B) nounwind { ; CHECK-LABEL: sqshl8b: ; CHECK: // %bb.0: _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
