================
@@ -270,6 +270,12 @@ def G_URSHR: AArch64GenericInstruction {
let hasSideEffects = 0;
}
+def G_VSLI: AArch64GenericInstruction {
----------------
JoshdRod wrote:There's an SRI that isn't supported yet - should I also add a test case to this file? https://github.com/llvm/llvm-project/pull/171448 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
