================
@@ -787,18 +788,19 @@ bool RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
// field offset in low and size in high 16 bits.
// Src1 Hi16|Lo16 = Size|FieldOffset
- auto Mask = B.buildConstant(SgprRB_S32, maskTrailingOnes<unsigned>(6));
- auto FieldOffset = B.buildAnd(SgprRB_S32, LSBit, Mask);
- auto Size = B.buildShl(SgprRB_S32, Width, B.buildConstant(SgprRB_S32, 16));
- auto Src1 = B.buildOr(SgprRB_S32, FieldOffset, Size);
+ auto Mask = B.buildConstant(SgprRB_I32, maskTrailingOnes<unsigned>(6));
+ auto FieldOffset = B.buildAnd(SgprRB_I32, LSBit, Mask);
+ auto Size = B.buildShl(SgprRB_I32, Width, B.buildConstant(SgprRB_I32, 16));
+ auto Src1 = B.buildOr(SgprRB_I32, FieldOffset, Size);
unsigned Opc32 = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
unsigned Opc64 = Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64;
unsigned Opc = Ty == S32 ? Opc32 : Opc64;
// Select machine instruction, because of reg class constraining, insert
// copies from reg class to reg bank.
- auto S_BFE = B.buildInstr(Opc, {{SgprRB, Ty}},
- {B.buildCopy(Ty, Src), B.buildCopy(S32, Src1)});
+ auto S_BFE =
+ B.buildInstr(Opc, {{SgprRB, Ty}},
+ {B.buildCopy(Ty, Src), B.buildCopy(LLT::integer(32),
Src1)});
----------------
chinmaydd wrote:
```suggestion
{B.buildCopy(Ty, Src), B.buildCopy(I32, Src1)});
```
https://github.com/llvm/llvm-project/pull/208270
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