================
@@ -1242,7 +1245,7 @@ bool RegBankLegalizeHelper::lowerAbsToNegMax(MachineInstr
&MI) {
Register Zero;
if (Ty == V2S16) {
// buildConstant cannot produce a V2S16 directly; pack two S16 zeros.
- Register Zero16 = B.buildConstant({VgprRB, S16}, 0).getReg(0);
+ Register Zero16 = B.buildConstant({VgprRB, LLT::integer(16)}, 0).getReg(0);
----------------
chinmaydd wrote:
Can introduce `I16` for `LLT::integer(16)`
https://github.com/llvm/llvm-project/pull/208270
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