http://llvm.org/bugs/show_bug.cgi?id=7791
Summary: Invalid(?) ldr instruction form is disassembled as eor
Product: new-bugs
Version: trunk
Platform: PC
OS/Version: Linux
Status: NEW
Severity: normal
Priority: P
Component: new bugs
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
(trunk rev 110038)
Opcode
002a78d4
is disassembled by llvm as
eoreq r7, r10, r4, asr r8
However note that bit 7 is always 0 in eor register-shifted-register, so this
is not eor:
cond 0000 001S nnnn dddd ssss 0tt1 mmmm
^
0000 0000 0010 1010 0111 1000 1101 0100
^
The opcode seems to be, in fact, ldrdeq (register), and both objdump and
libdisarm disassemble it as 'ldrdeq r7, [r10], -r4':
cond 000P U0W0 nnnn tttt (0000) 1101 mmmm
0000 0000 0010 1010 0111 1000 1101 0100
(I assume the bits in parenthesis mean that's the form assemblers should
output, as I cannot find an explanation in the ARM reference manual.)
However, here P=0 and W=1, and the reference manual says that case is
'UNPREDICTABLE'.
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