On 01/21/2015 02:44 PM, Petr Machata wrote: > So it seems to me this logic should be folded into mips_next_pcs, and > only activated when the stepped-over instruction is an LL. ... > I think ltrace currently support two breakpoints for software > singlestep. So you put one just after the SC, and one extra is > available for when there's a jump between LL and SC. If there are more > jumps, we just don't have a good answer for that. PowerPC just gives up > and returns SWS_FAIL, which should at least clean up things and get > ltrace into the right states.
PPC sets breakpoints at branch destination for all branches within the atomic sequence and relies on the call-back to handle more than 1 jumps as an error. If we fold the atomic logic in to mips_next_pc, we'd have to remove checks on (nr <= 2) from mips_next_pc and allow it to return more than 2 addresses. Does this sound reasonable? > makes me think, what if I have a code like this (pardon pseudo-assembly, > I don't actually speak MIPS ;) ) > > JMP xyz > LL > ... etc ... > xyz: > SC I can't find the relevant spec for whether this is valid, but gcc does not allow LL in a delay slot; it will always insert padding after the jump. Anyway, if this was allowed, there would be no way to handle it while single stepping. PC never actually points to the instruction in the delay slot so there would be no way to determine the beginning of the atomic sequence except by explicit inspecting PC+4, while inspecting the branch instruction. I am thinking of doing 2 scans: first to establish the range of the atomic sequence and the next to check for branches going out side of this range. I will incorporate your loop restructuring and formatting suggestions. Thanks for the feedback. Regards, Faraz Shahbazker _______________________________________________ Ltrace-devel mailing list [email protected] http://lists.alioth.debian.org/cgi-bin/mailman/listinfo/ltrace-devel
