Hi David/Matheu, Yes, It was my mistake. I am sorry about that.
Here is my back ported working patch for 2.6.32 with lttng patch set 0.188 on MIPS architecture CAVM octeon plus (52xx, 58xx) boards. ============================================================================================== >From abd8fb81cc1aea87a2867736251d1be15e02a51c Mon Sep 17 00:00:00 2001 From: Naresh Bhat <[email protected]> Date: Wed, 16 Feb 2011 18:00:19 +0530 Subject: [PATCH] fix lttng mips use 64 bit counter for trace clock, get_cycles on octeon --- arch/mips/Kconfig | 7 ++++ arch/mips/include/asm/octeon/trace-clock.h | 43 ++++++++++++++++++++++++++++ arch/mips/include/asm/timex.h | 35 ++++++++++++++++++++++- arch/mips/include/asm/trace-clock.h | 5 +++ arch/mips/kernel/smp.c | 2 + 5 files changed, 91 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/octeon/trace-clock.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2aaf0a3..8e19a6d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1739,10 +1739,17 @@ config CPU_R4400_WORKAROUNDS config HAVE_GET_CYCLES_32 def_bool y depends on !CPU_R4400_WORKAROUNDS + depends on !CPU_CAVIUM_OCTEON select HAVE_TRACE_CLOCK select HAVE_TRACE_CLOCK_32_TO_64 select HAVE_UNSYNCHRONIZED_TSC +config HAVE_GET_CYCLES + def_bool y + depends on CPU_CAVIUM_OCTEON + select HAVE_TRACE_CLOCK + select HAVE_UNSYNCHRONIZED_TSC + # # Use the generic interrupt handling code in kernel/irq/: # diff --git a/arch/mips/include/asm/octeon/trace-clock.h b/arch/mips/include/asm/octeon/trace-clock.h new file mode 100644 index 0000000..41345a7 --- /dev/null +++ b/arch/mips/include/asm/octeon/trace-clock.h @@ -0,0 +1,43 @@ +/* +** Copyright (C) 2005,2008 Mathieu Desnoyers +** +** Trace clock MIPS Octeon definitions. +**/ + +#ifndef _ASM_MIPS_OCTEON_TRACE_CLOCK_H +#define _ASM_MIPS_OCTEON_TRACE_CLOCK_H + +#include <asm/octeon/octeon.h> + +#define TC_HW_BITS 64 + +static inline u32 trace_clock_read32(void) +{ + return (u32)read_c0_cvmcount(); /* only need the 32 LSB */ +} + +static inline u64 trace_clock_read64(void) +{ + return read_c0_cvmcount(); +} + +static inline u64 trace_clock_frequency(void) +{ + return octeon_get_clock_rate(); +} + +static inline u32 trace_clock_freq_scale(void) +{ + return 1; +} + +static inline void get_trace_clock(void) +{ + return; +} +static inline void put_trace_clock(void) +{ + return; +} +#endif /* _ASM_MIPS_OCTEON_TRACE_CLOCK_H */ + diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h index 10c8dd8..13256b4 100644 --- a/arch/mips/include/asm/timex.h +++ b/arch/mips/include/asm/timex.h @@ -42,9 +42,42 @@ extern unsigned int mips_hpt_frequency; * will result in the timer interrupt getting lost. */ +#if defined(CONFIG_CPU_CAVIUM_OCTEON) +/* Since the Octeon supports a 64 bit cycle counter we might as well use + * it. We can't use it with an O32 kernel since 64bit registers are not + * saved. */ +typedef unsigned long cycles_t; +#else typedef unsigned int cycles_t; +#endif + +#ifdef CONFIG_HAVE_GET_CYCLES +# ifdef CONFIG_CPU_CAVIUM_OCTEON +static inline cycles_t get_cycles(void) +{ + return read_c0_cvmcount(); +} + +static inline void get_cycles_barrier(void) +{ +} + +static inline cycles_t get_cycles_rate(void) +{ + return mips_hpt_frequency; +} + +extern int test_tsc_synchronization(void); +extern int _tsc_is_sync; +static inline int tsc_is_sync(void) +{ + return _tsc_is_sync; +} +# else /* #ifdef CONFIG_CPU_CAVIUM_OCTEON */ +# error "64-bit get_cycles() supported only on Cavium Octeon MIPS architectures" +# endif /* #else #ifdef CONFIG_CPU_CAVIUM_OCTEON */ +#elif defined(CONFIG_HAVE_GET_CYCLES_32) -#ifdef CONFIG_HAVE_GET_CYCLES_32 static inline cycles_t get_cycles(void) { return read_c0_count(); diff --git a/arch/mips/include/asm/trace-clock.h b/arch/mips/include/asm/trace-clock.h index 3d8cb0f..3c9c638 100644 --- a/arch/mips/include/asm/trace-clock.h +++ b/arch/mips/include/asm/trace-clock.h @@ -12,6 +12,10 @@ #define TRACE_CLOCK_MIN_PROBE_DURATION 200 +#ifdef CONFIG_CPU_CAVIUM_OCTEON +# include <asm/octeon/trace-clock.h> +#else /* !CONFIG_CPU_CAVIUM_OCTEON */ + /* * Number of hardware clock bits. The higher order bits are expected to be 0. * If the hardware clock source has more than 32 bits, the bits higher than the @@ -65,6 +69,7 @@ static inline void put_trace_clock(void) { put_synthetic_tsc(); } +#endif /* CONFIG_CPU_CAVIUM_OCTEON */ static inline void set_trace_clock_is_sync(int state) { diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index f8c50d1..42083eb 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -159,7 +159,9 @@ void __init smp_cpus_done(unsigned int max_cpus) { mp_ops->cpus_done(); synchronise_count_master(); +#ifdef CONFIG_HAVE_UNSYNCHRONIZED_TSC test_tsc_synchronization(); +#endif } /* called from main before smp_init() */ -- 1.6.3.3.209.g83a28 ============================================================================================== * * *Thanks and Regards* *-Naresh Bhat* On Thu, Feb 17, 2011 at 12:10 AM, Mathieu Desnoyers < [email protected]> wrote: > * David Daney ([email protected]) wrote: > > On 02/16/2011 03:26 AM, Naresh Bhat wrote: > >> Hi Mathieu/David, > >> > >> Thank you very much for all your support. > >> Here is my back ported working patch for 2.6.32 with lttng patch set > 0.188 > >> kernel > >> > >> > ==================================================================================================== > >> Description: > >> > >> fix lttng mips use 64 bit counter for trace clock > >> and fix octeon get_cycles > >> > >> Signed-off-by: David Daney<[email protected]> > > > > I don't recall being the author of this patch, nor having really been > > associated with it in any way. > > > > Did someone other than me add my Signed-off-by: header? If so, please > > remove it. > > Hi David, > > It looks like Naresh mistakenly attributed both of us with sign-off. > This is a patch being posted for older lttng versions, so it won't end > up in any LTTng tree. But Naresh should repost it without our sign-offs > > >> Signed-off-by: Mathieu Desnoyers<[email protected]> > > (to remove too) > > since this is code that has been produced by him. > > Naresh: See the Linux kernel Documentation/SubmittingPatches, section 12 > for details. > > Thanks, > > Mathieu > > >> Signed-off-by: Naresh Bhat<[email protected]> > >> --- > >> arch/mips/Kconfig | 7 ++++ > >> arch/mips/include/asm/octeon/trace-clock.h | 43 > >> ++++++++++++++++++++++++++++ > >> arch/mips/include/asm/timex.h | 35 > ++++++++++++++++++++++- > >> arch/mips/include/asm/trace-clock.h | 6 ++++ > >> arch/mips/kernel/smp.c | 2 + > >> 5 files changed, 92 insertions(+), 1 deletions(-) > >> create mode 100644 arch/mips/include/asm/octeon/trace-clock.h > >> > > > > -- > Mathieu Desnoyers > Operating System Efficiency R&D Consultant > EfficiOS Inc. > http://www.efficios.com >
_______________________________________________ ltt-dev mailing list [email protected] http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
