Are the RD*, WR* and IO/M* signals OK? They go through a buffer M20 before being used. The ROM CS- only relies on A15, STROM- & IO/M-, if IO/M- is stuck at 0, then CS would work, but the I/O ports would not be accessed. Holding the 80C85 is reset should allow the outputs of M20 to go high, the inputs have pull-ups.
If the ‘245 M2 data bus buffer direction is not changed by RD* then the processor might be reading garbage from the data bus. All of the Address Decoding is done on the upper 8 Address bits so the chip selects do not depend on AD0-AD7 buffers. On boot there is a 10,000 cycle loop (approx 100ms delay) before there is I/O activity setting up the 81C55. This might be the 'The ROM /CS is also toggling for a while after reset’ state you are observing, any idea how long the activity lasts? After that the IO/M- line should start to toggle as the 81C55 is set up and the keyboard read. The first RAM access occurs after all the I/O is configured and the keyboard scanned. If you see no IO/M* activity after the short delay then the processor could be reading invalid data and just not executing any IN/OUT operations. There could be a few reasons for this: faulty buffer M20, faulty M2, address conflict another CS/CE line could be low at the same time, bad ROM socket or failing ROM. Check that all the CE– lines (M4 only one RAM module present) are high and none are low, also check that none of the I/O port enables (M16) are low during the ROM CS-. Might want to make sure these chips also have VDD present. I would read the ROM in situ. If you can clip onto M2 it should be possible to check that the 80C85 is really getting the data from the ROM. It should be possible to get this down to a single failed IC or track without pulling chips :-D From: M100 <[email protected]<mailto:[email protected]>> on behalf of Jeffrey Birt <[email protected]<mailto:[email protected]>> Reply-To: <[email protected]<mailto:[email protected]>> Date: Friday, May 4, 2018 at 5:21 AM To: <[email protected]<mailto:[email protected]>> Subject: Re: [M100] SPAM-LOW: Re: New member - question on 'half' alive Model 100 I did find some time last evening to investigate my sick M100 further. All A/D signals seem to be propagating through the buffers/latches properly and make their way to they ROM. The ROM /CS is also toggling for a while after reset is pressed so it does seem it is being accessed. It just occurred to me though that I failed to check the various RAM /CExx bank select signals. I guess after checking out the RAM /CExx signals I could get out my little logic analyzer and monitor the data buss after a reset and see if the ROM seems to be returning the correct data, or I’ll just build an adapter, so I can read it in. I also just recalled that my little eprom programmer can test many 74xx style logic chips so if I run completely out of ideas I can do a semi-shot gun approach and pull the glue logic chips and test them. Jeff
