On 11/1/2020 8:18 PM, Stephen Adolph wrote:
You have to multiply by 2. The input frequency to the processor is 2x
the cpu speed
Stock is 4.9152 MHz.
So yes , but x2.. implication is a pretty fast cpld. I think the xcr
family at 7ns may just do it.
To cut down on required CPU speed, consider this IC to do the heavy lifting:
https://www.digikey.com/en/products/detail/diodes-incorporated/PT7C4511WE/5226936
It might work with a 2.4576MHz crystal/clock, but it claims a minimum of
5MHz. If <5Mhz works, that speed would general the following /2 CPU speeds:
2.4576 3.072 3.6864 4.096 4.9152 6.144 6.5536 7.3728 9.8304
If it must use a 5MHz+clock, I'd use a 9.8304 oscillator and use the
CPLD to /4 the resulting output from the multiplier. That might help
with CPLD speed selection. I've used the unit before, and it's a nice
compact solution. Using 9.8304 +- 1.2288MHz might give you some better
options as well.
Then the CPLD can just implement an IO latch on the 8085 bus to set the
divisor, and when set, the unit will probably need to reset. If the
output clock signal is fed back into the CPLD enroute to the 8085, you
could conceivably stretch the clock periods for LCD IO access, making
8MHz workable.
Jim
