To continue the exploration on overclock, I have assembled a proper clock synthesizer which can generate any clock from 2.5M to 10M. It uses a 74HC4046 PLL chip, a 10 divider and a 250kHz to 1MHz source clock.
So this will let me finely tweak clock period to try and estimate safe overclock. My approach will be as follows. 1. I need a way to measure time-to-failure. To this end I have an IPL program that measures and displays time. When the program crashes I can use the last time displayed as data. 2. Plotting clock cycle time vs. Failure time should produce a curve that will allow extrapolation the fastest safe clock rate. I would think log(failure time) vs linear(cycle time) would be a straight line.
