So it's a way to replace the lost function of RAMRST since we're
clobbering that?
That's pretty neat.
--
bkw
On 8/30/22 00:05, Stephen Adolph wrote:
Thought I would post this.
The following snip is from a variant of QUAD I was working on.
I wanted to have a "ram protect" function and I decided that I could
generate something by detecting ALE pulses. When ALE is active, RAM
needs to be available. Otherwise switch off the RAM.
Here's the circuit.
* the 2N7002 FET discharges the cap C2 when ALE is pulsing
* when no ALE, C2 charges up via R1.
image.png
This is what power-up looked like.
ALE pulses in RED, /ACTIVE in blue. It takes about 20 ALE pulses to
enable the RAM, which is maybe 7 instructions at most.
M100 OS is barely getting started and has not accessed the RAM yet.
image.png
Anyhow, a suggestion to consider for ram protection.
Steve
On Sun, Aug 28, 2022 at 9:37 AM Stephen Adolph <[email protected]
<mailto:[email protected]>> wrote:
Henner, thanks for that measurement. That's good data.
So yeah it does seem unreasonable to pull A* around.
Seems to leave only RAMRST.
I did create a circuit that uses ALE to generate a signal "ram
active" indicating when the processor is running. It works as a ram
protect ckt. I will post that.
--
bkw
