The INST_READ flag is only being set in the detailed cpu model. If you
are using the simple cpu model (cpu/simple/cpu.cc) you will need to set
the flag of the mem_req before you issue the fetch request and change it
back when you issue a non instruction fetch.
If you go into cpu/simple/cpu.cc you will need to add a line that says:
memReq->flags |= INST_READ;
This should be placed before the icacheInterface->access(memReq) call.
You should also place the following line before all the instances of the
dcacheInterface->access(memReq) calls (there are three of them I believe):
memReq->flags &= ~INST_READ;
-Ron
On Thu, 1 Dec 2005, Anupama Kunchakara wrote:
Thanx Ronald for ur instant reply about data/instruction ..
I tried that , but iam always getting false for the [ req->isInstRead()
]
So is it like its always data or am i going wrong somwhere..
In the config file i have written
root.L1 = DL1Cache(in_bus=NULL,out_bus=Parent.toL2Bus)
root.L1 = IL1Cache(in_bus=NULL,out_bus=Parent.toL2Bus)
where root = Root()
I used this in_bus=NULL..is this reason why iam not able to differentiate
between inst and data..does this have anything to with instruction and
data..??
Ur response will be appreciated..
Thank you
Anupama
Graduate Student
Computer Science Department
(Webmaster for Lamar Career Center)
Lamar University
Texas
-------------------------------------------------------
This SF.net email is sponsored by: Splunk Inc. Do you grep through log files
for problems? Stop! Download the new AJAX search engine that makes
searching your log files as easy as surfing the web. DOWNLOAD SPLUNK!
http://ads.osdn.com/?ad_id=7637&alloc_id=16865&op=click
_______________________________________________
m5sim-users mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/m5sim-users
