If you are not running in timing mode for the memory then there is an bug where the flags are not copied. This can be fixed by copying the flags to the busReq object in Cache<>::probe().
in_bus = null lets us know that this is an L1 cache and constructs it to interface with a CPU object. Erik On Mon, 5 Dec 2005, Anupama Kunchakara wrote: > Thanx Ronald for ur instant reply about data/instruction .. > > I tried that , but iam always getting false for the [ req->isInstRead() > ] > So is it like its always data or am i going wrong somewhere.. > > And Nathan..u told me that it over writes...I tried to do this.. > > In the config file i have written > > root.*DL1* = *DL1*Cache(in_bus=*Parent.toDL1Bus*,out_bus=Parent.toL2Bus) > root.*IL1* = *IL1*Cache(in_bus=*Parent.toIL1Bus*,out_bus=Parent.toL2Bus) > > I tried this too..but still iam not able to differentiate. > Is it not the way ? If not then whats is the solution ? > > And why do we use in_bus = NULL..what does that mean ?? > > Ur response will be appreciated.. > > Thank you > > > -- > Anupama > Graduate Student > Computer Science Department > (Webmaster for Lamar Career Center) > Lamar University > Texas > ------------------------------------------------------- This SF.net email is sponsored by: Splunk Inc. Do you grep through log files for problems? Stop! Download the new AJAX search engine that makes searching your log files as easy as surfing the web. DOWNLOAD SPLUNK! http://ads.osdn.com/?ad_id=7637&alloc_id=16865&op=click _______________________________________________ m5sim-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/m5sim-users
