[m5sim-users] data/instruction

[Anupama Kunchakara]

Thankyou so much for your instant replies..

As the second assignment si overwriting the first in this statements..

> root.L1 = DL1Cache(in_bus=NULL,out_bus=Parent.toL2Bus )
> root.L1 = IL1Cache(in_bus=NULL,out_bus=Parent.toL2Bus)

Can we write in this way

> root.DL1 = DL1Cache(in_bus=Parent.toL1Bus,out_bus=Parent.toL2Bus)
> root.IL1 = IL1Cache(in_bus=Parent.toL1Bus,out_bus=Parent.toL2Bus)
 

can we create this two bus objects ??

and could you please tell me why do we put in_bus=NULL(what does that mean??)

Thank you
Anupama
 

you also need to have one name be root.IL1 and another root.DL1,
otherwise, you only actually get one cache because the second assignment
overwrites the first.

  Nathan

--
Anupama
Graduate Student
Computer Science Department
(Webmaster for Lamar Career Center)
Lamar University
Texas