Re: [m5sim-users] Understanding of cache implementation on write?

Wed, 14 Dec 2005 21:26:01 -0800
Note that handleMiss only calls allocateWrite if the access is a write *and* either it's uncacheable, the writeAllocate flag is false, or it's a "no response" request (that is, a writeback). If you track it down to cache_builder.cc you'll see that the writeAllocate flag is always true. So on standard cacheable writes, that code is skipped and allocateMiss is called instead. 

Please send all your questions to the m5sim-users list, not directly to me.

Magic Zheng wrote:


Dear Sir,

 
Sorry for the disturbance. I am still confused on how M5 send a block 
*read* request to the next level of cache/main memory.

 From my understanding, if there is a write miss, the process is like

¡°Cache::access <http://m5.eecs.umich.edu/docs/classCache.html#a2>¡± ¨¤ 
¡°MissQueue::handleMiss 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#a5>¡± ¨¤ 
¡°MissQueue::allocateWrite 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#d1>¡± ¨¤ 
¡°BaseCache::setMasterRequest¡± ¨¤ ¡°BusInterface 
<http://m5.eecs.umich.edu/docs/classBusInterface.html>::request 
<http://m5.eecs.umich.edu/docs/classBaseInterface.html#a2>¡± ¨¤ 
¡°Bus::requestAddrBus <http://m5.eecs.umich.edu/docs/classBus.html#a4>¡±.
 
In the function ¡°MissQueue::allocateWrite 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#d1>¡±


00384     cache <http://m5.eecs.umich.edu/docs/classMissQueue.html#p6>->setMasterRequest 
<http://m5.eecs.umich.edu/docs/classBaseCache.html#a11>(Request_WB 
<http://m5.eecs.umich.edu/docs/base__cache_8hh.html#a11a7>, time 
<http://m5.eecs.umich.edu/docs/tsunami__io_8cc.html#a1>);


There is only a ¡°Request_WB¡± which is sent to the BUS. Could you give 
me some hints where the ¡°write¡± command is translated to the ¡°read¡± 
command and the ¡°read¡± command is sent to the next level cache/memory?
 
Your help are highly appreciated!
 
Magic
 


MSHR <http://m5.eecs.umich.edu/docs/classMSHR.html>*

00346 <http://m5.eecs.umich.edu/docs/classMissQueue.html#d0> MissQueue::allocateMiss 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#d0>(MemReqPtr 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html> &req, int size, Tick time)

00347
 {

00348     MSHR <http://m5.eecs.umich.edu/docs/classMSHR.html>* mshr = mq 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p0>.allocate 
<http://m5.eecs.umich.edu/docs/classMSHRQueue.html#a5>(req, size 
<http://m5.eecs.umich.edu/docs/alpha__memory_8cc.html#a1>);

00349     mshr->order <http://m5.eecs.umich.edu/docs/classMSHR.html#o7> = order 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p9>++;

00350     if (!req->isUncacheable() ){//&& !req->isNoAllocate()) {

00351         // Mark this as a cache line fill

00352         mshr->req 
<http://m5.eecs.umich.edu/docs/classMSHR.html#o4>->flags |= CACHE_LINE_FILL;

00353     }

00354     if (mq <http://m5.eecs.umich.edu/docs/classMissQueue.html#p0>.isFull 
<http://m5.eecs.umich.edu/docs/classMSHRQueue.html#a16>()) {

00355         cache <http://m5.eecs.umich.edu/docs/classMissQueue.html#p6>->setBlocked 
<http://m5.eecs.umich.edu/docs/classBaseCache.html#a7>(Blocked_NoMSHRs 
<http://m5.eecs.umich.edu/docs/base__cache_8hh.html#a10a0>);

00356     }

00357     if (req->cmd != Hard_Prefetch) {

00358         //If we need to request the bus (not on HW prefetch), do so

00359         cache <http://m5.eecs.umich.edu/docs/classMissQueue.html#p6>->setMasterRequest 
<http://m5.eecs.umich.edu/docs/classBaseCache.html#a11>(Request_MSHR 
<http://m5.eecs.umich.edu/docs/base__cache_8hh.html#a11a6>, time 
<http://m5.eecs.umich.edu/docs/tsunami__io_8cc.html#a1>);

00360     }

00361     return mshr;

00362 }


00363 

00364 


00365 MSHR <http://m5.eecs.umich.edu/docs/classMSHR.html>*

00366 <http://m5.eecs.umich.edu/docs/classMissQueue.html#d1> MissQueue::allocateWrite 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#d1>(MemReqPtr 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html> &req, int size, Tick time)

00367 {

00368     MSHR <http://m5.eecs.umich.edu/docs/classMSHR.html>* mshr = wb 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p1>.allocate 
<http://m5.eecs.umich.edu/docs/classMSHRQueue.html#a5>(req,req->size);

00369     mshr->order <http://m5.eecs.umich.edu/docs/classMSHR.html#o7> = order 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p9>++;

00370     if (cache <http://m5.eecs.umich.edu/docs/classMissQueue.html#p6>->doData 
<http://m5.eecs.umich.edu/docs/classBaseHier.html#a1>()){

00371         if (req->isCompressed()) {

00372             delete [] mshr->req 
<http://m5.eecs.umich.edu/docs/classMSHR.html#o4>->data 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html#p0>;


00373            
 mshr->req <http://m5.eecs.umich.edu/docs/classMSHR.html#o4>->actualSize = req->actualSize;


00374             mshr->req <http://m5.eecs.umich.edu/docs/classMSHR.html#o4>->data 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html#p0> = new uint8_t[req->actualSize];

00375             memcpy(mshr->req <http://m5.eecs.umich.edu/docs/classMSHR.html#o4>->data 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html#p0>, req->data 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html#p0>, req->actualSize);

00376         } else {

00377             memcpy(mshr->req <http://m5.eecs.umich.edu/docs/classMSHR.html#o4>->data 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html#p0>, req->data 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html#p0>, req->size);


00378         }   


00379     }

00380     if (wb <http://m5.eecs.umich.edu/docs/classMissQueue.html#p1>.isFull 
<http://m5.eecs.umich.edu/docs/classMSHRQueue.html#a16>()) {

00381         cache <http://m5.eecs.umich.edu/docs/classMissQueue.html#p6>->setBlocked 
<http://m5.eecs.umich.edu/docs/classBaseCache.html#a7>(Blocked_NoWBBuffers 
<http://m5.eecs.umich.edu/docs/base__cache_8hh.html#a10a2>);

00382     }


00383 


00384     cache <http://m5.eecs.umich.edu/docs/classMissQueue.html#p6>->setMasterRequest 
<http://m5.eecs.umich.edu/docs/classBaseCache.html#a11>(Request_WB 
<http://m5.eecs.umich.edu/docs/base__cache_8hh.html#a11a7>, time 
<http://m5.eecs.umich.edu/docs/tsunami__io_8cc.html#a1>);


00385 


00386     return mshr;

00387 }


00388 

00389 


!
 00393 void

00394 <http://m5.eecs.umich.edu/docs/classMissQueue.html#a5> MissQueue::handleMiss 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#a5>(MemReqPtr 
<http://m5.eecs.umich.edu/docs/classRefCountingPtr.html> &req, int blkSize, Tick time)

00395 {

00396 //    if (!cache->isTopLevel())

00397     if (prefetchMiss) prefetcher 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p7>->handleMiss 
<http://m5.eecs.umich.edu/docs/classBasePrefetcher.html#a4>(req, time 
<http://m5.eecs.umich.edu/docs/tsunami__io_8cc.html#a1>);


00398 


00399     int size <http://m5.eecs.umich.edu/docs/alpha__memory_8cc.html#a1> = 
blkSize;

00400     Addr <http://m5.eecs.umich.edu/docs/isa__traits_8hh.html#a3> blkAddr = 
req->paddr & ~(Addr)(blkSize-1);

00401     MSHR <http://m5.eecs.umich.edu/docs/classMSHR.html>* mshr = NULL;


00402    
 if (!req->isUncacheable()) {


00403         mshr = mq 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p0>.findMatch 
<http://m5.eecs.umich.edu/docs/classMSHRQueue.html#a2!
 >(blkAddr, req->asid);

00404         if (mshr) {

00405             //@todo remove hw_pf here

00406             mshr_hits 
<http://m5.eecs.umich.edu/docs/group__CacheStatistics.html#ga25>[req->cmd.toIndex()][req->thread_num]++;

00407             if (mshr->threadNum 
<http://m5.eecs.umich.edu/docs/classMSHR.html#o3> != req->thread_num) {

00408                 mshr->!
 threadNum <http://m5.eecs.umich.edu/docs/classMSHR.html#o3> = -1;

00409             }

00410             mq 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p0>.allocateTarget 
<http://m5.eecs.umich.edu/docs/classMSHRQueue.html#a9>(mshr, req);

00411           !

 ; 
 if (mshr->req <http://m5.eecs.umich.edu/docs/classMSHR.html#o4>->isNoAllocate() && !req->isNoAllocate()) {


00412               !

  
 //We are adding an allocate after a no-allocate


00413                 mshr->req 
<http://m5.eecs.umich.edu/docs/classMSHR.html#o4>->!
 ;flags
 &= ~NO_ALLOCATE;

00414             }

00415             if (mshr->getNumTargets 
<http://m5.eecs.umich.edu/docs/classMSHR.html#a6>() == numTarget) {

0!
 0416                 noTargetMSHR 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#r0> = mshr;

00417                 cache 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p6>->setBlocked 
<http://m5.eecs.umich.edu/docs/classBaseCache.html#a7>(Blocked_NoTargets 
<http://m5.eecs.umich.edu/docs/base__cache_8hh.html#a10a1>);

00418                 mq 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p0>.moveToFront 
<http://m5.eecs.umich.edu/docs/classMSHRQueue.html#a11>(mshr);

00419             }

00420             return;

00421         }

00422         if (req->isNoAllocate()) {

00423             //Count no-allocate requests differently

00424             mshr_no_allocate_misses 
<http://m5.eecs.umich.edu/docs/group__CacheStatistics.html#ga51>++;

00425         }

00426         else {

00427             mshr_misses 
<http://m5.eecs.umich.edu/docs/group__CacheStatistics.html#ga28>[req->cmd.toIndex()][req->thread_num]++;

00428         }

00429     } else {

00430         //Count uncacheable accesses

00431         mshr_uncacheable 
<http://m5.eecs.umich.edu/docs/group__CacheStatistics.html#ga31>[req->cmd.toIndex()][req->thread_num]++;

00432         size <http://m5.eecs.umich.edu/docs/alpha__memory_8cc.html#a1> = 
req->size;

00433     }

00434     if (req->cmd.isWrite() && (req->isUncacheable() || !writeAllocate 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#p5> ||


00435                               
 req->cmd.isNoResponse())) {


00439         mshr = allocateWrite 
<http://m5.eecs.umich.edu/docs/classMissQueue.html#d1>(req, req->size, time 
<http://m5.eecs.umich.edu/docs/tsunami__io_8cc.html#a1>);

00440         return;

00441     }


00442 


00443     mshr = allocateMiss <http://m5.eecs.umich.edu/docs/classMissQueue.html#d0>(req, 
size <http://m5.eecs.umich.edu/docs/alpha__memory_8cc.html#a1>, time 
<http://m5.eecs.umich.edu/docs/tsunami__io_8cc.html#a1>);

00444 }



*/Steve Reinhardt <[EMAIL PROTECTED]>/* wrote:


    The caches are write allocate: in the case of a write miss, an MSHR
    entry will be allocated and a block *read* request will be issued to
    the
    next level of cache to do the fill.

    Steve

    Magic Zheng wrote:
     >
     > Dear Sir,
     >
     > I want to confirm the understanding of cache implementation on
    write.
     > For each level cache (L1 and L2), if there are write hits on
    cache, we
     > tag the cache block dirty. However, if there are write misses; we
     > allocate an entry on MSHR and try to write through to next level
    memory.
     > (Here we do not allocate a cache block and read the content from the
     > next level memory?) Could you please point my understanding is
    correct
     > or not? If yes, it will create many writes to next level memory;
    could
     > you e! xplain the intention here?
     >
     > Thank you for your time?
     >
     > Magic.
     >
     >
    ------------------------------------------------------------------------
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     >
     > >


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