It depends on what you mean by "correctly" :-). Functionally I believe
they do work, i.e. you should be getting results of some semantically
legal execution, but the timing is unfortunately not modeled, so those
results may well not match what a real machine with the same timing
would get.
One confusing situation is that the functional LL/SC behavior for SE
mode is implemented in encumbered/mem/functional/main.{cc,hh}, while in
FS mode it got pulled up into ExecContext (since FS mode uses a
different type of main memory object). However instead of moving it up
to ExecContext for SE also, it got left in the memory object. Bleah.
Yet another thing we're hoping to have fixed up for 2.0...
Steve
Jeff wrote:
I forgot to add that I am working in ALPHA_SE mode.
it looks like it's not, when looking at the exec_context.hh file with the
write() function.
jeff
-----Original Message-----
From: Jeff <[EMAIL PROTECTED]>
Sent: Mar 10, 2006 2:30 PM
To: m5 <[email protected]>
Subject: [m5sim-users] LL-SC instructions
I was wondering if load locked/link and store conditional instructions are
being modeled correctly in functional and detailed CPUs.
it looks like they aren't in what i'm doing, but i just want to make sure if
that's the problem or not, since i've spent the past two weeks narrowing down
this bug to that.
thanks
jeff
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