That does look like a bug. Thanks for tracking it down.
Can you post your patch to the list or put it on Sourceforge?
Thanks,
Steve
Jeff wrote:
i think that req->result isn't being updated always correctly. when the list is empty, you just return a boolean false, but without setting the req->result flag. also, when the list doesn't contain and tracked load-locked, you also retrun a boolean false without setting the req->result flag.
so after i added those modifications, i now can get things working, so it kinda
seems that's what should be going on.
-----Original Message-----
From: Jeff <[EMAIL PROTECTED]>
Sent: Mar 10, 2006 6:29 PM
To: Steve Reinhardt <[EMAIL PROTECTED]>
Cc: m5 <[email protected]>
Subject: Re: [m5sim-users] LL-SC instructions
sorry... disregard my last comment.
i see the flag getting cleared when traversing the locklist.
-----Original Message-----
From: Steve Reinhardt <[EMAIL PROTECTED]>
Sent: Mar 10, 2006 6:10 PM
To: Jeff <[EMAIL PROTECTED]>
Cc: m5 <[email protected]>
Subject: Re: [m5sim-users] LL-SC instructions
Note that req->result gets set in MainMemory::checkLockedAddrList().
Jeff wrote:
Actually, it looks like it partially works. the stq_c doesn't write if the lock_flag was cleared, however it seems that the register is not getting the correct value, i.e. a zero in case the write was not performed. it seems that it always gets a one.
-----Original Message-----
From: Jeff <[EMAIL PROTECTED]>
Sent: Mar 10, 2006 2:30 PM
To: m5 <[email protected]>
Subject: [m5sim-users] LL-SC instructions
I was wondering if load locked/link and store conditional instructions are
being modeled correctly in functional and detailed CPUs.
it looks like they aren't in what i'm doing, but i just want to make sure if
that's the problem or not, since i've spent the past two weeks narrowing down
this bug to that.
thanks
jeff
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