Actually, it looks like it partially works. the stq_c doesn't write if the lock_flag was cleared, however it seems that the register is not getting the correct value, i.e. a zero in case the write was not performed. it seems that it always gets a one.
-----Original Message----- >From: Jeff <[EMAIL PROTECTED]> >Sent: Mar 10, 2006 2:30 PM >To: m5 <[email protected]> >Subject: [m5sim-users] LL-SC instructions > >I was wondering if load locked/link and store conditional instructions are >being modeled correctly in functional and detailed CPUs. > >it looks like they aren't in what i'm doing, but i just want to make sure if >that's the problem or not, since i've spent the past two weeks narrowing down >this bug to that. > >thanks >jeff > > >------------------------------------------------------- >This SF.Net email is sponsored by xPML, a groundbreaking scripting language >that extends applications into web and mobile media. Attend the live webcast >and join the prime developer group breaking into this new coding territory! >http://sel.as-us.falkag.net/sel?cmd=lnk&kid=110944&bid=241720&dat=121642 >_______________________________________________ >m5sim-users mailing list >[email protected] >https://lists.sourceforge.net/lists/listinfo/m5sim-users ------------------------------------------------------- This SF.Net email is sponsored by xPML, a groundbreaking scripting language that extends applications into web and mobile media. Attend the live webcast and join the prime developer group breaking into this new coding territory! http://sel.as-us.falkag.net/sel?cmd=lnk&kid=110944&bid=241720&dat=121642 _______________________________________________ m5sim-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/m5sim-users
