Re: [m5sim-users] Syscall Emulation Memory

[Mishali Naik]

I was wondering if the implementation of L2 can be modified from being shared to behave like a private L2 in a CMP setting with the existing coherence protocol?
Thanks for your help.

Mishali
Undergraduate Student,
UCLA

Steve Reinhardt <[EMAIL PROTECTED]> wrote:

Can you be more specific? The L2 cache only has a single input port,
but you can use a bus to connect multiple L1s to that.

Mishali Naik wrote:
> Hi All,
> I have been looking at the memory hierarchy in Syscall
> emulation. The current implementation has a bus connecting the master
> interface of on chip cache to the L2 cache. Is it possible to change
> this interface between the chip and the L2 ie can more ports be added to
> the L2 ? I would really appreciate any kind of help.
> Thanks,
> Mishali
>
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