Mishali,
Currently the coherence protocol will only work at the first level of
caches (no private L2's). The limitation is that the CSHR structure is
set up only to send DMA Invalidates up the memory hierarchy. In order to
extend the current model to support private L2's you would need to find a
way to send snoops in each private L2 to the L1's that are above it.
This sounds simple enough, but with events enabled in the memory system
this also means that you will have to be careful about requests crossing
paths(i.e. a L2 snoops a invalidate from another L2 and forwards it up to
the L1 but at the same time the L1 sends a upgrade out. You would need to
have some method for NACKing the upgrade request, and have that L1 retry
again).
In short, if you don't wish to model the memory heirarchy with
timing(atomic memory model) then you could extend the protocol by either
forwarding all requests snooped by the L2's to the L1's above it, or
sending just the ones the L1 needs (if you force inclusion this makes the
coherence traffic less, or if you have some sort of filter to remove
irrelevant snoop forwarding).
-Ron
On Fri, 7 Apr 2006, Mishali Naik wrote:
I was wondering if the implementation of L2 can be modified from being shared
to behave like a private L2 in a CMP setting with the existing coherence
protocol?
Thanks for your help.
Mishali
Undergraduate Student,
UCLA
Steve Reinhardt <[EMAIL PROTECTED]> wrote:
Can you be more specific? The L2 cache only has a single input port,
but you can use a bus to connect multiple L1s to that.
Mishali Naik wrote:
Hi All,
I have been looking at the memory hierarchy in Syscall
emulation. The current implementation has a bus connecting the master
interface of on chip cache to the L2 cache. Is it possible to change
this interface between the chip and the L2 ie can more ports be added to
the L2 ? I would really appreciate any kind of help.
Thanks,
Mishali
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