Suppose in my simulation i have L1 cache and no L2.
Now i want some request to access cache but some
should be forced to go to network as if there is no
L1.
How to do this efficiently?
In cpu.cc there is a boolean variable called do_access
which is stated to control cache access. But in the
code there is nothing mentioned what happens do_access
is false:
/*
if (do_access) {
if (!dcachePort.sendTiming(dcache_pkt)) {
_status = DcacheRetry;
} else {
_status = DcacheWaitResponse;
// memory system takes ownership of packet
dcache_pkt = NULL;
}
}
*/
--- Steve Reinhardt <[EMAIL PROTECTED]> escribió:
> Did you look in m5stats.txt? If you don't have
> cache stats in there,
> it's because you're running a configuration with no
> caches.
>
> Steve
>
> On Nov 19, 2007 5:49 AM, abc def
> <[EMAIL PROTECTED]> wrote:
> > Is there a quick way to generate statistics after
> > running a program in m5, for example how many tlb
> > misses, page faults, l1 miss, l2 miss etc for
> simple
> > or timing cpu?
> >
> >
> >
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