Thanks again Charles,
Yeah, I got the same measurement value as you mentioned and summarized as
below:
JP1 header:
Pin 15 : Z Dir
Pin 16 : Z STEP
Pin 15 : Y Dir
Pin 16 : Y STEP
Pin 15 : X Dir
Pin 16 : X STEP
I am going to connect it to step driver A4988 soon and see how.
Best regards!
-chengxi
On Sun, Mar 19, 2017 at 7:38 PM, Charles Steinkuehler <
[email protected]> wrote:
> Refer to the DE0-Nano-SoC schematic (found on the CD-ROM:
> http://www.terasic.com/downloads/cd-rom/de0-nano-soc/) and you will
> see that the signal GPIO_0 16 is physically on header JP1, pin 19 and
> signal GPIO_0 17 is physically on header JP1, pin 20.
>
> In addition to the different starting pin number (0 vs. 1), the JP1
> header has some power and ground pins between groups of I/O signals,
> which isn't mentioned in the User's Guide.
>
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