> > I imagine you could significantly speed up the code by keeping
> much of the
> > data in register. REG-REG operations take a lot less time than
> a REG-MEM
> > operation. Should be delicious.
>
> From what I understand of Merced, compiler technology is going to be the
> problem. It's probably not unreasonable to expect large performance
> increases as the intelligence of compilers (especially the "free"
> compilers like gcc and egcs) catches up to the theoretical performance
> of the CPU.
Well, I hope George can do some assembly for the Merced. It'll be a pain
though, I'm sure, having to do all those new optimizations by hand.
As for the compilers, remember that RISC type architecture is nothing really
new...and EPIC type stuff has been around a while. There are already
compilers for other systems that contain much of the brains to do the
optimizations already...they just need to get those smarts moved over to
IA64's particular needs.
And what with Intel making IA64 "simulators" available way before samples of
Merced ever ship, the software vendors have had ample time to work with
it...meaning that when Merced does ship in volume, the software *should*
hopefully be ready.
Aaron
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