> As for the compilers, remember that RISC type architecture is nothing
really
> new...and EPIC type stuff has been around a while. There are already
> compilers for other systems that contain much of the brains to do the
> optimizations already...they just need to get those smarts moved over to
> IA64's particular needs.
IA64 is really VLIW (very long instruction word), which is quite different
than traditional sequential RISC. It requires the compiler to do a LOT of
massively parallel pipeline scheduling to achieve optimal results. HP has a
leg up on this compiler technology as IA64 is based on their existing
PA-RISC, and is sharing there compiler backend optimzation technology with
Intel and Microsoft.
Having once programmed a VLIW machine in 'assembler', I would not wish that
task on ANYONE. The machine I worked on had 8 parallel asymetrical
execution units, and a 288 bit wide opcode which launched 8 parallel
different instructions in every cycle. The assembler (micro?) coder had to
keep track of which parts of what execution unit would take how long to do
each instruction, and not rely on results before they were ready. To keep
the machine actually humming along at even close to half its theoretical
performance levels bordered on nightmarish.
-jrp
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