On Thu, Mar 16, 2017 at 4:17 PM, Chad Versace <[email protected]> wrote:
> On Wed 15 Mar 2017, Jason Ekstrand wrote: > > On Mon, Mar 13, 2017 at 3:28 PM, Chad Versace <[email protected]> > > wrote: > > > > > --- > > > src/intel/isl/isl.h | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h > > > index 9d92906ca71..b79793b0c93 100644 > > > --- a/src/intel/isl/isl.h > > > +++ b/src/intel/isl/isl.h > > > @@ -473,6 +473,9 @@ typedef uint32_t isl_tiling_flags_t; > > > /** The Skylake BSpec refers to Yf and Ys as "standard tiling > formats". */ > > > #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \ > > > ISL_TILING_Ys_BIT) > > > + > > > +#define ISL_TILING_AUX_MASK (ISL_TILING_HIZ_BIT | \ > > > + ISL_TILING_CCS_BIT) > > > > > > > What about MCS? > > Right. This is bad code. > > How about I test against ISL_SURF_USAGE_{HIZ,MCS,CCS_D,CCS_E} instead? > In the next patch, where it matters? > Sure. Either works so long as you include all the AUX bits. --Jason
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