---
src/amd/common/ac_nir_to_llvm.c | 63 +++++++++++++++++++++++++----------------
src/amd/common/ac_shader_abi.h | 12 ++++++++
2 files changed, 51 insertions(+), 24 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 3869161967d..ad2c2336ee8 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2759,79 +2759,78 @@ load_tcs_output(struct nir_to_llvm_context *ctx,
value[i] = ac_lds_load(&ctx->ac, dw_addr);
dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
ctx->ac.i32_1, "");
}
result = ac_build_varying_gather_values(&ctx->ac, value,
instr->num_components, comp);
result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir,
&instr->dest.ssa), "");
return result;
}
static void
-store_tcs_output(struct nir_to_llvm_context *ctx,
- nir_intrinsic_instr *instr,
+store_tcs_output(struct ac_shader_abi *abi,
+ LLVMValueRef vertex_index,
+ LLVMValueRef param_index,
+ unsigned const_index,
+ unsigned location,
+ unsigned driver_location,
LLVMValueRef src,
+ unsigned component,
+ bool is_patch,
+ bool is_compact,
unsigned writemask)
{
+ struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
LLVMValueRef dw_addr;
LLVMValueRef stride = NULL;
LLVMValueRef buf_addr = NULL;
- LLVMValueRef vertex_index = NULL;
- LLVMValueRef indir_index = NULL;
- unsigned const_index = 0;
unsigned param;
- const unsigned comp = instr->variables[0]->var->data.location_frac;
- const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var,
ctx->stage);
- const bool is_compact = instr->variables[0]->var->data.compact;
bool store_lds = true;
- if (instr->variables[0]->var->data.patch) {
- if (!(ctx->tcs_patch_outputs_read & (1U <<
instr->variables[0]->var->data.location)))
+ if (is_patch) {
+ if (!(ctx->tcs_patch_outputs_read & (1U << location)))
store_lds = false;
} else {
- if (!(ctx->tcs_outputs_read & (1ULL <<
instr->variables[0]->var->data.location)))
+ if (!(ctx->tcs_outputs_read & (1ULL << location)))
store_lds = false;
}
- get_deref_offset(ctx->nir, instr->variables[0],
- false, NULL, per_vertex ? &vertex_index : NULL,
- &const_index, &indir_index);
- param =
shader_io_get_unique_index(instr->variables[0]->var->data.location);
- if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0
&&
+ param = shader_io_get_unique_index(location);
+ if (location == VARYING_SLOT_CLIP_DIST0 &&
is_compact && const_index > 3) {
const_index -= 3;
param++;
}
- if (!instr->variables[0]->var->data.patch) {
+ if (!is_patch) {
stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
dw_addr = get_tcs_out_current_patch_offset(ctx);
} else {
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
}
- mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
+ mark_tess_output(ctx, is_patch, param);
dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact,
vertex_index, stride,
- indir_index);
+ param_index);
buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
is_compact,
- vertex_index, indir_index);
+ vertex_index, param_index);
bool is_tess_factor = false;
- if (instr->variables[0]->var->data.location ==
VARYING_SLOT_TESS_LEVEL_INNER ||
- instr->variables[0]->var->data.location ==
VARYING_SLOT_TESS_LEVEL_OUTER)
+ if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
+ location == VARYING_SLOT_TESS_LEVEL_OUTER)
is_tess_factor = true;
unsigned base = is_compact ? const_index : 0;
for (unsigned chan = 0; chan < 8; chan++) {
if (!(writemask & (1 << chan)))
continue;
- LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan -
comp);
+ LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan -
component);
if (store_lds || is_tess_factor)
ac_lds_store(&ctx->ac, dw_addr, value);
if (!is_tess_factor && writemask != 0xF)
ac_build_buffer_store_dword(&ctx->ac,
ctx->hs_ring_tess_offchip, value, 1,
buf_addr, ctx->oc_lds,
4 * (base + chan), 1, 0,
true, false);
dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
@@ -3127,21 +3126,36 @@ visit_store_var(struct ac_nir_context *ctx,
for (unsigned chan = 0; chan < 4; chan++) {
if (old_writemask & (1 << chan))
writemask |= 3u << (2 * chan);
}
}
switch (instr->variables[0]->var->data.mode) {
case nir_var_shader_out:
if (ctx->stage == MESA_SHADER_TESS_CTRL) {
- store_tcs_output(ctx->nctx, instr, src, writemask);
+ LLVMValueRef vertex_index = NULL;
+ LLVMValueRef indir_index = NULL;
+ unsigned const_index = 0;
+ const unsigned location =
instr->variables[0]->var->data.location;
+ const unsigned driver_location =
instr->variables[0]->var->data.driver_location;
+ const unsigned comp =
instr->variables[0]->var->data.location_frac;
+ const bool is_patch =
instr->variables[0]->var->data.patch;
+ const bool is_compact =
instr->variables[0]->var->data.compact;
+
+ get_deref_offset(ctx, instr->variables[0],
+ false, NULL, is_patch ? NULL :
&vertex_index,
+ &const_index, &indir_index);
+
+ ctx->abi->store_tcs_outputs(ctx->abi, vertex_index,
indir_index,
+ const_index, location,
driver_location,
+ src, comp, is_patch,
is_compact, writemask);
return;
}
for (unsigned chan = 0; chan < 8; chan++) {
int stride = 4;
if (!(writemask & (1 << chan)))
continue;
value = llvm_extract_elem(&ctx->ac, src, chan - comp);
@@ -6579,20 +6593,21 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.num_output_culls =
shaders[i]->info.cull_distance_array_size;
if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
ctx.gs_next_vertex = ac_build_alloca(&ctx.ac,
ctx.ac.i32, "gs_next_vertex");
ctx.gs_max_out_vertices =
shaders[i]->info.gs.vertices_out;
ctx.abi.load_inputs = load_gs_input;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
ctx.tcs_patch_outputs_read =
shaders[i]->info.patch_outputs_read;
ctx.abi.load_tess_inputs = load_tcs_input;
+ ctx.abi.store_tcs_outputs = store_tcs_output;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode =
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_inputs = load_tes_input;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
ctx.shader_info->vs.vgpr_comp_cnt =
MAX2(3,
ctx.shader_info->vs.vgpr_comp_cnt);
}
} else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
shader_info->fs.can_discard =
shaders[i]->info.fs.uses_discard;
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index f22a6a001e5..c4d9926e82b 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -78,20 +78,32 @@ struct ac_shader_abi {
LLVMValueRef param_index,
unsigned const_index,
unsigned location,
unsigned driver_location,
LLVMTypeRef type,
unsigned component,
unsigned num_components,
bool is_patch,
bool is_compact);
+ void (*store_tcs_outputs)(struct ac_shader_abi *abi,
+ LLVMValueRef vertex_index,
+ LLVMValueRef param_index,
+ unsigned const_index,
+ unsigned location,
+ unsigned driver_location,
+ LLVMValueRef src,
+ unsigned component,
+ bool is_patch,
+ bool is_compact,
+ unsigned writemask);
+
LLVMValueRef (*load_ubo)(struct ac_shader_abi *abi, LLVMValueRef index);
/**
* Load the descriptor for the given buffer.
*
* \param buffer the buffer as presented in NIR: this is the descriptor
* in Vulkan, and the buffer index in OpenGL/Gallium
* \param write whether buffer contents will be written
*/
LLVMValueRef (*load_ssbo)(struct ac_shader_abi *abi,
--
2.14.3
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