From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_descriptors.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 5083027..76f2a3e 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -2053,89 +2053,90 @@ void si_shader_change_notify(struct si_context *sctx)
R_00B330_SPI_SHADER_USER_DATA_ES_0);
else
si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
R_00B130_SPI_SHADER_USER_DATA_VS_0);
} else {
si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
}
}
static void si_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
- struct si_descriptors *desc,
- unsigned sh_base,
+ unsigned sh_offset,
unsigned pointer_count)
{
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count *
(HAVE_32BIT_POINTERS ? 1 : 2), 0));
- radeon_emit(cs, (sh_base + desc->shader_userdata_offset -
SI_SH_REG_OFFSET) >> 2);
+ radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
}
static void si_emit_shader_pointer_body(struct si_screen *sscreen,
struct radeon_winsys_cs *cs,
- struct si_descriptors *desc)
+ uint64_t va)
{
- uint64_t va = desc->gpu_address;
-
radeon_emit(cs, va);
if (HAVE_32BIT_POINTERS)
assert((va >> 32) == sscreen->info.address32_hi);
else
radeon_emit(cs, va >> 32);
}
static void si_emit_shader_pointer(struct si_context *sctx,
struct si_descriptors *desc,
unsigned sh_base)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ unsigned sh_offset = sh_base + desc->shader_userdata_offset;
- si_emit_shader_pointer_head(cs, desc, sh_base, 1);
- si_emit_shader_pointer_body(sctx->screen, cs, desc);
+ si_emit_shader_pointer_head(cs, sh_offset, 1);
+ si_emit_shader_pointer_body(sctx->screen, cs, desc->gpu_address);
}
static void si_emit_consecutive_shader_pointers(struct si_context *sctx,
unsigned pointer_mask,
unsigned sh_base)
{
if (!sh_base)
return;
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
while (mask) {
int start, count;
u_bit_scan_consecutive_range(&mask, &start, &count);
struct si_descriptors *descs = &sctx->descriptors[start];
+ unsigned sh_offset = sh_base + descs->shader_userdata_offset;
- si_emit_shader_pointer_head(cs, descs, sh_base, count);
+ si_emit_shader_pointer_head(cs, sh_offset, count);
for (int i = 0; i < count; i++)
- si_emit_shader_pointer_body(sctx->screen, cs, descs +
i);
+ si_emit_shader_pointer_body(sctx->screen, cs,
+ descs[i].gpu_address);
}
}
static void si_emit_disjoint_shader_pointers(struct si_context *sctx,
unsigned pointer_mask,
unsigned sh_base)
{
if (!sh_base)
return;
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
while (mask) {
struct si_descriptors *descs =
&sctx->descriptors[u_bit_scan(&mask)];
+ unsigned sh_offset = sh_base + descs->shader_userdata_offset;
- si_emit_shader_pointer_head(cs, descs, sh_base, 1);
- si_emit_shader_pointer_body(sctx->screen, cs, descs);
+ si_emit_shader_pointer_head(cs, sh_offset, 1);
+ si_emit_shader_pointer_body(sctx->screen, cs,
descs->gpu_address);
}
}
static void si_emit_global_shader_pointers(struct si_context *sctx,
struct si_descriptors *descs)
{
if (sctx->b.chip_class == GFX9) {
/* Broadcast it to all shader stages. */
si_emit_shader_pointer(sctx, descs,
R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
--
2.7.4
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