From: Marek Olšák <marek.ol...@amd.com>
TCS_OUT_LAYOUT has 13 unused bits. That's enough for a 32-bit address
aligned to 512KB. Hey, it's a 13-bit pointer!
---
src/gallium/drivers/radeonsi/si_shader.c | 104 +++++++++++-----------
src/gallium/drivers/radeonsi/si_shader.h | 6 +-
src/gallium/drivers/radeonsi/si_shader_internal.h | 4 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 8 +-
src/gallium/drivers/radeonsi/si_state_shaders.c | 39 ++------
5 files changed, 70 insertions(+), 91 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 0bf5228..786b250 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1168,42 +1168,60 @@ static LLVMValueRef lds_load(struct
lp_build_tgsi_context *bld_base,
static void lds_store(struct si_shader_context *ctx,
unsigned dw_offset_imm, LLVMValueRef dw_addr,
LLVMValueRef value)
{
dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
LLVMConstInt(ctx->i32, dw_offset_imm, 0));
ac_lds_store(&ctx->ac, dw_addr, value);
}
-static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
- unsigned param)
+enum si_tess_ring {
+ TCS_OFFCHIP_RING,
+ TCS_FACTOR_RING,
+ TES_OFFCHIP_RING,
+};
+
+static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
+ enum si_tess_ring ring)
{
LLVMBuilderRef builder = ctx->ac.builder;
-
+ unsigned param = ring == TES_OFFCHIP_RING ? ctx->param_tes_offchip_addr
:
+
ctx->param_tcs_out_lds_layout;
LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
- addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
- addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
- uint64_t desc2 = 0xffffffff;
- uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
- S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
- S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
- S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
- LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
+ /* TCS only receives high 13 bits of the address. */
+ if (ring == TCS_OFFCHIP_RING || ring == TCS_FACTOR_RING) {
+ addr = LLVMBuildAnd(builder, addr,
+ LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
+ }
+
+ if (ring == TCS_FACTOR_RING) {
+ unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
+ addr = LLVMBuildAdd(builder, addr,
+ LLVMConstInt(ctx->i32, tf_offset, 0), "");
+ }
- LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
- desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
- desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
- return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
+ LLVMValueRef desc[4];
+ desc[0] = addr;
+ desc[1] = LLVMConstInt(ctx->i32,
+
S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
+ desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
+ desc[3] = LLVMConstInt(ctx->i32,
+ S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+ S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+
S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
+
+ return ac_build_gather_values(&ctx->ac, desc, 4);
}
static LLVMValueRef fetch_input_tcs(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type, unsigned swizzle)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef dw_addr, stride;
@@ -1299,21 +1317,21 @@ static LLVMValueRef fetch_output_tcs(
}
static LLVMValueRef fetch_input_tes(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type, unsigned swizzle)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef buffer, base, addr;
- buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
+ buffer = get_tess_ring_descriptor(ctx, TES_OFFCHIP_RING);
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
buffer, base, addr, true);
}
LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
LLVMValueRef vertex_index,
@@ -1326,21 +1344,21 @@ LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi
*abi,
bool is_patch,
bool is_compact,
bool load_input)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct tgsi_shader_info *info = &ctx->shader->selector->info;
LLVMValueRef buffer, base, addr;
driver_location = driver_location / 4;
- buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
+ buffer = get_tess_ring_descriptor(ctx, TES_OFFCHIP_RING);
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
if (param_index) {
/* Add the constant index to the indirect index */
param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
LLVMConstInt(ctx->i32, const_index,
0), "");
} else {
param_index = LLVMConstInt(ctx->i32, const_index, 0);
}
@@ -1407,21 +1425,21 @@ static void store_output_tcs(struct
lp_build_tgsi_context *bld_base,
name == TGSI_SEMANTIC_TESSOUTER) {
/* The epilog doesn't read LDS if invocation 0
defines tess factors. */
skip_lds_store =
!sh_info->reads_tessfactor_outputs &&
ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
is_tess_factor = true;
is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
}
}
}
- buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
+ buffer = get_tess_ring_descriptor(ctx, TCS_OFFCHIP_RING);
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
uint32_t writemask = reg->Register.WriteMask;
while (writemask) {
chan_index = u_bit_scan(&writemask);
LLVMValueRef value = dst[chan_index];
if (inst->Instruction.Saturate)
@@ -1522,21 +1540,21 @@ static void si_nir_store_output_tcs(struct
ac_shader_abi *abi,
name == TGSI_SEMANTIC_TESSOUTER) {
/* The epilog doesn't read LDS if invocation 0
defines tess factors. */
skip_lds_store =
!info->reads_tessfactor_outputs &&
ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
is_tess_factor = true;
is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
}
}
}
- buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
+ buffer = get_tess_ring_descriptor(ctx, TCS_OFFCHIP_RING);
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
vertex_index,
param_index,
driver_location,
info->output_semantic_name,
info->output_semantic_index,
is_patch);
for (unsigned chan = 0; chan < 4; chan++) {
@@ -1969,21 +1987,21 @@ static LLVMValueRef si_load_tess_coord(struct
ac_shader_abi *abi)
return lp_build_gather_values(&ctx->gallivm, coord, 4);
}
static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
unsigned semantic_name)
{
LLVMValueRef buffer, base, addr;
int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
- buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
+ buffer = get_tess_ring_descriptor(ctx, TES_OFFCHIP_RING);
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
LLVMConstInt(ctx->i32, param, 0));
return buffer_load(&ctx->bld_base, ctx->f32,
~0, buffer, base, addr, true);
}
@@ -2993,21 +3011,21 @@ static void si_llvm_export_vs(struct si_shader_context
*ctx,
* for the fixed function TCS.
*/
static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef invocation_id, buffer, buffer_offset;
LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
uint64_t inputs;
invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
- buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
+ buffer = get_tess_ring_descriptor(ctx, TCS_OFFCHIP_RING);
buffer_offset = LLVMGetParam(ctx->main_fn,
ctx->param_tcs_offchip_offset);
lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
lds_vertex_stride, "");
lds_base = get_tcs_in_current_patch_offset(ctx);
lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset,
"");
inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
while (inputs) {
@@ -3127,21 +3145,21 @@ static void si_write_tess_factors(struct
lp_build_tgsi_context *bld_base,
}
/* Convert the outputs to vectors for stores. */
vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
vec1 = NULL;
if (stride > 4)
vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
/* Get the buffer. */
- buffer = desc_from_addr_base64k(ctx,
ctx->param_tcs_factor_addr_base64k);
+ buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
/* Get the offset. */
tf_base = LLVMGetParam(ctx->main_fn,
ctx->param_tcs_factor_offset);
byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
LLVMConstInt(ctx->i32, 4 * stride, 0), "");
lp_build_if(&inner_if_ctx, &ctx->gallivm,
LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
rel_patch_id, ctx->i32_0, ""));
@@ -3167,21 +3185,21 @@ static void si_write_tess_factors(struct
lp_build_tgsi_context *bld_base,
ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
stride - 4, byteoffset, tf_base,
offset, 1, 0, true, false);
/* Store the tess factors into the offchip buffer if TES reads them. */
if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
LLVMValueRef tf_inner_offset;
unsigned param_outer, param_inner;
- buf = desc_from_addr_base64k(ctx,
ctx->param_tcs_offchip_addr_base64k);
+ buf = get_tess_ring_descriptor(ctx, TCS_OFFCHIP_RING);
base = LLVMGetParam(ctx->main_fn,
ctx->param_tcs_offchip_offset);
param_outer = si_shader_io_get_unique_index_patch(
TGSI_SEMANTIC_TESSOUTER, 0);
tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id,
NULL,
LLVMConstInt(ctx->i32, param_outer, 0));
outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
util_next_power_of_two(outer_comps));
@@ -3286,35 +3304,31 @@ static void si_llvm_emit_tcs_epilogue(struct
ac_shader_abi *abi,
invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values,
blocks);
}
/* Return epilog parameters from this function. */
LLVMValueRef ret = ctx->return_value;
unsigned vgpr;
if (ctx->screen->info.chip_class >= GFX9) {
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_layout,
8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
- ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_addr_base64k,
- 8 +
GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
- ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_factor_addr_base64k,
- 8 +
GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
+ ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_out_lds_layout,
+ 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
/* Tess offchip and tess factor offsets are at the beginning. */
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_offset, 2);
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_factor_offset, 4);
- vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
+ vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
} else {
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_layout,
GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
- ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_addr_base64k,
- GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
- ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_factor_addr_base64k,
- GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
+ ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_out_lds_layout,
+ GFX6_SGPR_TCS_OUT_LAYOUT);
/* Tess offchip and tess factor offsets are after user SGPRs. */
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_offchip_offset,
GFX6_TCS_NUM_USER_SGPR);
ret = si_insert_input_ret(ctx, ret,
ctx->param_tcs_factor_offset,
GFX6_TCS_NUM_USER_SGPR + 1);
vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
}
/* VGPRs */
rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
@@ -3370,24 +3384,20 @@ static void si_set_ls_return_value_for_tcs(struct
si_shader_context *ctx)
ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
#endif
ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
8 + GFX9_SGPR_TCS_OUT_OFFSETS);
ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
8 + GFX9_SGPR_TCS_OUT_LAYOUT);
- ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
- 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
- ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
- 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
vgpr++, "");
ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
vgpr++, "");
ctx->return_value = ret;
}
@@ -4666,22 +4676,20 @@ static void create_function(struct si_shader_context
*ctx)
declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
break;
case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
declare_global_desc_pointers(ctx, &fninfo);
declare_per_stage_desc_pointers(ctx, &fninfo, true);
ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
- ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
- ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
/* VGPRs */
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.tcs_patch_id);
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.tcs_rel_ids);
/* param_tcs_offchip_offset and param_tcs_factor_offset are
* placed after the user SGPRs.
*/
@@ -4713,22 +4721,20 @@ static void create_function(struct si_shader_context
*ctx)
ctx->type ==
PIPE_SHADER_VERTEX);
declare_vs_specific_input_sgprs(ctx, &fninfo);
if (!HAVE_32BIT_POINTERS) {
declare_samplers_and_images(ctx, &fninfo,
ctx->type ==
PIPE_SHADER_TESS_CTRL);
}
ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
- ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
- ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
/* VGPRs (first TCS, then VS) */
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.tcs_patch_id);
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.tcs_rel_ids);
if (ctx->type == PIPE_SHADER_VERTEX) {
declare_vs_input_vgprs(ctx, &fninfo,
&num_prolog_vgprs);
/* LS return values are inputs to the TCS main shader
part. */
@@ -4736,21 +4742,21 @@ static void create_function(struct si_shader_context
*ctx)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 2; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
} else {
/* TCS return values are inputs to the TCS epilog.
*
* param_tcs_offchip_offset, param_tcs_factor_offset,
* param_tcs_offchip_layout, and param_rw_buffers
* should be passed to the epilog.
*/
- for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K;
i++)
+ for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 11; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
}
break;
case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
/* Merged stages have 8 system SGPRs at the beginning. */
/* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
if (HAVE_32BIT_POINTERS) {
@@ -4770,21 +4776,21 @@ static void create_function(struct si_shader_context
*ctx)
declare_global_desc_pointers(ctx, &fninfo);
declare_per_stage_desc_pointers(ctx, &fninfo,
(ctx->type ==
PIPE_SHADER_VERTEX ||
ctx->type ==
PIPE_SHADER_TESS_EVAL));
if (ctx->type == PIPE_SHADER_VERTEX) {
declare_vs_specific_input_sgprs(ctx, &fninfo);
} else {
/* TESS_EVAL (and also GEOMETRY):
* Declare as many input SGPRs as the VS has. */
ctx->param_tcs_offchip_layout = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
- ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
+ ctx->param_tes_offchip_addr = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
if (!HAVE_32BIT_POINTERS)
add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused
*/
ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR,
ctx->i32); /* unused */
}
if (!HAVE_32BIT_POINTERS) {
declare_samplers_and_images(ctx, &fninfo,
ctx->type ==
PIPE_SHADER_GEOMETRY);
@@ -4811,21 +4817,21 @@ static void create_function(struct si_shader_context
*ctx)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 5; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
}
break;
case PIPE_SHADER_TESS_EVAL:
declare_global_desc_pointers(ctx, &fninfo);
declare_per_stage_desc_pointers(ctx, &fninfo, true);
ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
- ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
+ ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
if (shader->key.as_es) {
ctx->param_tcs_offchip_offset = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
} else {
add_arg(&fninfo, ARG_SGPR, ctx->i32);
declare_streamout_params(ctx, &shader->selector->so,
&fninfo);
ctx->param_tcs_offchip_offset = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
@@ -7309,34 +7315,30 @@ static void si_build_tcs_epilog_function(struct
si_shader_context *ctx,
add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
if (!HAVE_32BIT_POINTERS)
add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
- add_arg(&fninfo, ARG_SGPR, ctx->i32);
- ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
- ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
+ ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
} else {
add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
+ ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
add_arg(&fninfo, ARG_SGPR, ctx->i32);
- add_arg(&fninfo, ARG_SGPR, ctx->i32);
- ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo,
ARG_SGPR, ctx->i32);
- ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR,
ctx->i32);
}
add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
unsigned tess_factors_idx =
add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the
wave (REL_PATCH_ID) */
add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch
*/
add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors
should be loaded from */
diff --git a/src/gallium/drivers/radeonsi/si_shader.h
b/src/gallium/drivers/radeonsi/si_shader.h
index e0d6f70..1b1f650 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -176,50 +176,46 @@ enum {
SI_SGPR_BASE_VERTEX,
SI_SGPR_START_INSTANCE,
SI_SGPR_DRAWID,
SI_SGPR_VS_STATE_BITS,
SI_VS_NUM_USER_SGPR,
SI_SGPR_VS_BLIT_DATA = SI_SGPR_CONST_AND_SHADER_BUFFERS,
/* TES */
SI_SGPR_TES_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
- SI_SGPR_TES_OFFCHIP_ADDR_BASE64K,
+ SI_SGPR_TES_OFFCHIP_ADDR,
SI_TES_NUM_USER_SGPR,
/* GFX6-8: TCS only */
GFX6_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
GFX6_SGPR_TCS_OUT_OFFSETS,
GFX6_SGPR_TCS_OUT_LAYOUT,
GFX6_SGPR_TCS_IN_LAYOUT,
- GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K,
- GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K,
GFX6_TCS_NUM_USER_SGPR,
/* GFX9: Merged shaders. */
#if HAVE_32BIT_POINTERS
/* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO (SGPR0). */
/* 2ND_SAMPLERS_AND_IMAGES is set in USER_DATA_ADDR_HI (SGPR1). */
GFX9_MERGED_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR,
#else
/* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO/HI
(SGPR[0:1]). */
GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES = SI_VS_NUM_USER_SGPR,
GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES_HI,
GFX9_MERGED_NUM_USER_SGPR,
#endif
/* GFX9: Merged LS-HS (VS-TCS) only. */
GFX9_SGPR_TCS_OFFCHIP_LAYOUT = GFX9_MERGED_NUM_USER_SGPR,
GFX9_SGPR_TCS_OUT_OFFSETS,
GFX9_SGPR_TCS_OUT_LAYOUT,
- GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K,
- GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K,
GFX9_TCS_NUM_USER_SGPR,
/* GS limits */
GFX6_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
GFX9_GS_NUM_USER_SGPR = GFX9_MERGED_NUM_USER_SGPR,
SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS + (HAVE_32BIT_POINTERS ? 1
: 2),
/* PS only */
SI_SGPR_ALPHA_REF = SI_NUM_RESOURCE_SGPRS,
SI_PS_NUM_USER_SGPR,
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index a9883d5..f9e0678 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -156,28 +156,28 @@ struct si_shader_context {
/* Offsets where TCS outputs and TCS patch outputs live in LDS:
* [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
* [16:31] = TCS output patch0 offset for per-patch / 16
* max = (NUM_PATCHES + 1) * 32*32
*/
int param_tcs_out_lds_offsets;
/* Layout of TCS outputs / TES inputs:
* [0:12] = stride between output patches in DW, num_outputs *
num_vertices * 4
* max = 32*32*4 + 32*4
* [13:18] = gl_PatchVerticesIn, max = 32
+ * [19:31] = high 13 bits of the 32-bit address of tessellation ring
buffers
*/
int param_tcs_out_lds_layout;
- int param_tcs_offchip_addr_base64k;
- int param_tcs_factor_addr_base64k;
int param_tcs_offchip_offset;
int param_tcs_factor_offset;
/* API TES */
+ int param_tes_offchip_addr;
int param_tes_u;
int param_tes_v;
int param_tes_rel_patch_id;
/* HW ES */
int param_es2gs_offset;
/* API GS */
int param_gs2vs_offset;
int param_gs_wave_id; /* GFX6 */
LLVMValueRef gs_vtx_offset[6]; /* in dwords (GFX6) */
int param_gs_vtx01_offset; /* in dwords (GFX9) */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 3881e3f..ad470fd 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -224,24 +224,28 @@ static void si_emit_derived_tess_state(struct si_context
*sctx,
/* Compute userdata SGPRs. */
assert(((input_vertex_size / 4) & ~0xff) == 0);
assert(((output_vertex_size / 4) & ~0xff) == 0);
assert(((input_patch_size / 4) & ~0x1fff) == 0);
assert(((output_patch_size / 4) & ~0x1fff) == 0);
assert(((output_patch0_offset / 16) & ~0xffff) == 0);
assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
assert(num_tcs_input_cp <= 32);
assert(num_tcs_output_cp <= 32);
+ uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
+ assert((ring_va & u_bit_consecutive(0, 19)) == 0);
+
tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
tcs_out_layout = (output_patch_size / 4) |
- (num_tcs_input_cp << 13);
+ (num_tcs_input_cp << 13) |
+ ring_va;
tcs_out_offsets = (output_patch0_offset / 16) |
((perpatch_output_offset / 16) << 16);
offchip_layout = *num_patches |
(num_tcs_output_cp << 6) |
(pervertex_output_patch_size * *num_patches << 12);
/* Compute the LDS size. */
lds_size = output_patch0_offset + output_patch_size * *num_patches;
if (sctx->b.chip_class >= CIK) {
@@ -289,21 +293,21 @@ static void si_emit_derived_tess_state(struct si_context
*sctx,
R_00B430_SPI_SHADER_USER_DATA_HS_0 +
GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
radeon_emit(cs, offchip_layout);
radeon_emit(cs, tcs_out_offsets);
radeon_emit(cs, tcs_out_layout);
radeon_emit(cs, tcs_in_layout);
}
/* Set userdata SGPRs for TES. */
radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
2);
radeon_emit(cs, offchip_layout);
- radeon_emit(cs, r600_resource(sctx->tess_rings)->gpu_address >> 16);
+ radeon_emit(cs, ring_va);
ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
if (sctx->b.chip_class >= CIK)
radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
ls_hs_config);
else
radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 57bf622..182f7c0 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2947,83 +2947,60 @@ static bool si_update_spi_tmpring_size(struct
si_context *sctx)
sctx->spi_tmpring_size = spi_tmpring_size;
si_mark_atom_dirty(sctx, &sctx->scratch_state);
}
return true;
}
static void si_init_tess_factor_ring(struct si_context *sctx)
{
assert(!sctx->tess_rings);
- /* Use 64K alignment for both rings, so that we can pass the address
- * to shaders as one SGPR containing bits [16:47].
+ /* The address must be aligned to 2^19, because the shader only
+ * receives the high 13 bits.
*/
sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen,
-
R600_RESOURCE_FLAG_UNMAPPABLE,
+ R600_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT,
-
align(sctx->screen->tess_offchip_ring_size,
- 64 * 1024) +
+
sctx->screen->tess_offchip_ring_size +
sctx->screen->tess_factor_ring_size,
- 64 * 1024);
+ 1 << 19);
if (!sctx->tess_rings)
return;
si_init_config_add_vgt_flush(sctx);
- uint64_t offchip_va = r600_resource(sctx->tess_rings)->gpu_address;
- assert((offchip_va & 0xffff) == 0);
- uint64_t factor_va = offchip_va +
- align(sctx->screen->tess_offchip_ring_size, 64 *
1024);
-
si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
+ uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
+ sctx->screen->tess_offchip_ring_size;
+
/* Append these registers to the init config state. */
if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
factor_va >> 8);
if (sctx->b.chip_class >= GFX9)
si_pm4_set_reg(sctx->init_config,
R_030944_VGT_TF_MEMORY_BASE_HI,
factor_va >> 40);
si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
sctx->screen->vgt_hs_offchip_param);
} else {
si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
factor_va >> 8);
si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
sctx->screen->vgt_hs_offchip_param);
}
- if (sctx->b.chip_class >= GFX9) {
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_LS_0 +
- GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
- offchip_va >> 16);
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_LS_0 +
- GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
- factor_va >> 16);
- } else {
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_HS_0 +
- GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
- offchip_va >> 16);
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_HS_0 +
- GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
- factor_va >> 16);
- }
-
/* Flush the context to re-emit the init_config state.
* This is done only once in a lifetime of a context.
*/
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
sctx->b.initial_gfx_cs_size = 0; /* force flush */
si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
}
/**
* This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
--
2.7.4
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