From: Marek Olšák <marek.ol...@amd.com>
so that it's not done multiple times in branches
---
src/gallium/drivers/radeonsi/si_shader.c | 21 +++++++++------------
src/gallium/drivers/radeonsi/si_shader_internal.h | 1 +
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 786b250..783d57f 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1315,51 +1315,47 @@ static LLVMValueRef fetch_output_tcs(
return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
dw_addr);
}
static LLVMValueRef fetch_input_tes(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type, unsigned swizzle)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
- LLVMValueRef buffer, base, addr;
-
- buffer = get_tess_ring_descriptor(ctx, TES_OFFCHIP_RING);
+ LLVMValueRef base, addr;
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
- buffer, base, addr, true);
+ ctx->tess_offchip_ring, base, addr, true);
}
LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
LLVMValueRef vertex_index,
LLVMValueRef param_index,
unsigned const_index,
unsigned location,
unsigned driver_location,
unsigned component,
unsigned num_components,
bool is_patch,
bool is_compact,
bool load_input)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct tgsi_shader_info *info = &ctx->shader->selector->info;
- LLVMValueRef buffer, base, addr;
+ LLVMValueRef base, addr;
driver_location = driver_location / 4;
- buffer = get_tess_ring_descriptor(ctx, TES_OFFCHIP_RING);
-
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
if (param_index) {
/* Add the constant index to the indirect index */
param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
LLVMConstInt(ctx->i32, const_index,
0), "");
} else {
param_index = LLVMConstInt(ctx->i32, const_index, 0);
}
@@ -1369,21 +1365,22 @@ LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi
*abi,
info->input_semantic_index,
is_patch);
/* TODO: This will generate rather ordinary llvm code, although it
* should be easy for the optimiser to fix up. In future we might want
* to refactor buffer_load(), but for now this maximises code sharing
* between the NIR and TGSI backends.
*/
LLVMValueRef value[4];
for (unsigned i = component; i < num_components + component; i++) {
- value[i] = buffer_load(&ctx->bld_base, ctx->i32, i, buffer,
base, addr, true);
+ value[i] = buffer_load(&ctx->bld_base, ctx->i32, i,
+ ctx->tess_offchip_ring, base, addr,
true);
}
return ac_build_varying_gather_values(&ctx->ac, value, num_components,
component);
}
static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_instruction *inst,
const struct tgsi_opcode_info *info,
unsigned index,
LLVMValueRef dst[4])
@@ -1983,32 +1980,30 @@ static LLVMValueRef si_load_tess_coord(struct
ac_shader_abi *abi)
PIPE_PRIM_TRIANGLES)
coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
lp_build_add(bld, coord[0], coord[1]));
return lp_build_gather_values(&ctx->gallivm, coord, 4);
}
static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
unsigned semantic_name)
{
- LLVMValueRef buffer, base, addr;
+ LLVMValueRef base, addr;
int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
- buffer = get_tess_ring_descriptor(ctx, TES_OFFCHIP_RING);
-
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
LLVMConstInt(ctx->i32, param, 0));
return buffer_load(&ctx->bld_base, ctx->f32,
- ~0, buffer, base, addr, true);
+ ~0, ctx->tess_offchip_ring, base, addr, true);
}
static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
unsigned varying_id)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
unsigned semantic_name;
switch (varying_id) {
@@ -5071,20 +5066,22 @@ static void preload_ring_buffers(struct
si_shader_context *ctx)
S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
S_008F0C_ELEMENT_SIZE(1) | /*
element_size = 4 (bytes) */
S_008F0C_INDEX_STRIDE(1) | /*
index_stride = 16 (elements) */
S_008F0C_ADD_TID_ENABLE(1),
0),
LLVMConstInt(ctx->i32, 3, 0), "");
ctx->gsvs_ring[stream] = ring;
}
+ } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
+ ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx,
TES_OFFCHIP_RING);
}
}
static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
LLVMValueRef param_rw_buffers,
unsigned param_pos_fixed_pt)
{
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef slot, desc, offset, row, bit, address[2];
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index f9e0678..4dab921 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -184,20 +184,21 @@ struct si_shader_context {
int param_gs_vtx23_offset; /* in dwords (GFX9) */
int param_gs_vtx45_offset; /* in dwords (GFX9) */
/* CS */
int param_block_size;
LLVMTargetMachineRef tm;
/* Preloaded descriptors. */
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring[4];
+ LLVMValueRef tess_offchip_ring;
LLVMValueRef invoc0_tess_factors[6]; /* outer[4], inner[2] */
LLVMValueRef gs_next_vertex[4];
LLVMValueRef postponed_kill;
LLVMValueRef return_value;
LLVMTypeRef voidt;
LLVMTypeRef i1;
LLVMTypeRef i8;
LLVMTypeRef i32;
--
2.7.4
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