Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/brw_program.c | 30 +++---------------------------
1 file changed, 3 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.c
index c121136c439..d1988ff620d 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -402,33 +402,9 @@ brw_alloc_stage_scratch(struct brw_context *brw,
if (devinfo->gen >= 9)
subslices = 4 * brw->screen->devinfo.num_slices;
- unsigned scratch_ids_per_subslice;
- if (devinfo->is_haswell) {
- /* WaCSScratchSize:hsw
- *
- * Haswell's scratch space address calculation appears to be sparse
- * rather than tightly packed. The Thread ID has bits indicating
- * which subslice, EU within a subslice, and thread within an EU it
- * is. There's a maximum of two slices and two subslices, so these
- * can be stored with a single bit. Even though there are only 10 EUs
- * per subslice, this is stored in 4 bits, so there's an effective
- * maximum value of 16 EUs. Similarly, although there are only 7
- * threads per EU, this is stored in a 3 bit number, giving an
- * effective maximum value of 8 threads per EU.
- *
- * This means that we need to use 16 * 8 instead of 10 * 7 for the
- * number of threads per subslice.
- */
- scratch_ids_per_subslice = 16 * 8;
- } else if (devinfo->is_cherryview) {
- /* For Cherryview, it appears that the scratch addresses for the 6 EU
- * devices may still generate compute scratch addresses covering the
- * same range as 8 EU.
- */
- scratch_ids_per_subslice = 8 * 7;
- } else {
- scratch_ids_per_subslice = devinfo->max_cs_threads;
- }
+ const unsigned scratch_ids_per_subslice =
+ devinfo->cs_scratch_ids_per_subslice ?
+ devinfo->cs_scratch_ids_per_subslice : devinfo->max_cs_threads;
thread_count = scratch_ids_per_subslice * subslices;
break;
--
2.16.1
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