On Wed, Jun 18, 2008 at 3:53 PM, Aapo Tahkola <[EMAIL PROTECTED]> wrote: > On Tue, 17 Jun 2008 11:56:00 +0200 > Nicolai Hähnle <[EMAIL PROTECTED]> wrote: > >> Hey Aapo, >> >> Am Dienstag 17 Juni 2008 04:07:01 schrieb Aapo Tahkola: >> > On Mon, 16 Jun 2008 12:56:39 +0200 >> > > Nicolai Hähnle <[EMAIL PROTECTED]> wrote: >> > > I want a compiler infrastructure that can do more than one pass >> > > over the program that is to be compiled. I also want to be able >> > > to do passes that are more complex than a linear walk through >> > > instructions while looking at only one instruction at a time. For >> > > example, I'm thinking of: >> > > - a very simple algorithm for dead code elimination that walks >> > > through the program *backwards* >> > > - an algorithm to merge MUL and ADD into MAD >> > >> > I once wrote an algo that had the ability to remove all write masks >> > and swizzles of all instructions that do not contribute to the >> > results. Simply dropping instructions with no write mask implements >> > dead code elimination. >> >> Did you publish that code somewhere? I was thinking of implementing >> the exact same thing some time in the future, but if you already have >> something like it that can be adapted... > > No, didn't release it. I'm not even sure if I still have it(blew couple > hard disks few years back). Have to check my desktop hds when I get a > chance.
I wrote similar code which now lives in the i965 driver in brw_wm_pass*.c. In short there is: brw_wm_fp.c -- various preprocessing simplifications to the mesa program representation. -- add instructions required by hw to set up interpolants, etc. brw_wm_pass0.c -- convert to an SSA format, but still very close to the mesa program instruction format. -- identify shared/scalar values (eg all 4 results of a DP3 instruction) -- discard non-saturating, non-negating swizzles and moves brw_wm_pass1.c -- dead code elimination -- basically clear writemask for unused values, on a scalar granularity brw_wm_pass2.c -- generate liveness information for each scalar register component -- register allocation, assuming a scalar or SOA architecture. Most of this code is independent of the i965 architecture, though assumptions do creep in... The big simplifying assumption is that we're talking about only ARB_fs style shaders - ie no loops or branches. Keith Keith ------------------------------------------------------------------------- Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php _______________________________________________ Mesa3d-dev mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/mesa3d-dev
