This patch makes render emit size prediction count the corect emit size.
Signed-off-by: Pauli Nieminen <[email protected]>
---
src/mesa/drivers/dri/r200/r200_state_init.c | 94 +++++++++++++++++----------
src/mesa/drivers/dri/radeon/radeon_common.c | 2 +-
2 files changed, 61 insertions(+), 35 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c
b/src/mesa/drivers/dri/r200/r200_state_init.c
index 5b8f394..2a1db80 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -329,9 +329,8 @@ static void mtl_emit(GLcontext *ctx, struct
radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
- uint32_t dwords = atom->cmd_size;
+ uint32_t dwords = atom->emit_size;
- dwords += 6;
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
@@ -342,9 +341,8 @@ static void lit_emit(GLcontext *ctx, struct
radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
- uint32_t dwords = atom->cmd_size;
+ uint32_t dwords = atom->emit_size;
- dwords += 8;
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
@@ -355,9 +353,8 @@ static void ptp_emit(GLcontext *ctx, struct
radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
- uint32_t dwords = atom->cmd_size;
+ uint32_t dwords = atom->emit_size;
- dwords += 8;
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
@@ -368,9 +365,8 @@ static void veclinear_emit(GLcontext *ctx, struct
radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
- uint32_t dwords = atom->cmd_size;
+ uint32_t dwords = atom->emit_size;
- dwords += 4;
OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
}
@@ -378,9 +374,8 @@ static void scl_emit(GLcontext *ctx, struct
radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
- uint32_t dwords = atom->cmd_size;
+ uint32_t dwords = atom->emit_size;
- dwords += 2;
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_SCL(atom->cmd[0], atom->cmd+1);
END_BATCH();
@@ -391,9 +386,8 @@ static void vec_emit(GLcontext *ctx, struct
radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
- uint32_t dwords = atom->cmd_size;
+ uint32_t dwords = atom->emit_size;
- dwords += 4;
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_VEC(atom->cmd[0], atom->cmd+1);
END_BATCH();
@@ -406,10 +400,10 @@ static void ctx_emit(GLcontext *ctx, struct
radeon_state_atom *atom)
struct radeon_renderbuffer *rrb;
uint32_t cbpitch;
uint32_t zbpitch, depth_fmt;
- uint32_t dwords = atom->cmd_size;
+ uint32_t dwords = atom->emit_size;
/* output the first 7 bytes of context */
- BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, 5);
rrb = radeon_get_depthbuffer(&r200->radeon);
@@ -629,12 +623,12 @@ static void cube_emit(GLcontext *ctx, struct
radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
- uint32_t dwords = 3;
+ uint32_t dwords = atom->emit_size;
int i = atom->idx, j;
radeonTexObj *t = r200->state.texture.unit[i].texobj;
radeon_mipmap_level *lvl;
- BEGIN_BATCH_NO_AUTOSTATE(dwords + (3 * 5));
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
/* XXX that size won't really match with image_override... */
OUT_BATCH_TABLE(atom->cmd, 2);
@@ -653,12 +647,12 @@ static void cube_emit_cs(GLcontext *ctx, struct
radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
- uint32_t dwords = 2;
+ uint32_t dwords = atom->emit_size;
int i = atom->idx, j;
radeonTexObj *t = r200->state.texture.unit[i].texobj;
radeon_mipmap_level *lvl;
- BEGIN_BATCH_NO_AUTOSTATE(dwords + (4 * 5));
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, 2);
if (t && !t->image_override) {
@@ -719,9 +713,15 @@ void r200InitState( r200ContextPtr rmesa )
ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
if (rmesa->radeon.radeonScreen->kernel_mm)
+ {
rmesa->hw.ctx.emit = ctx_emit_cs;
+ rmesa->hw.ctx.emit_size = 28;
+ }
else
+ {
rmesa->hw.ctx.emit = ctx_emit;
+ rmesa->hw.ctx.emit_size += 4;
+ }
ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
@@ -774,10 +774,13 @@ void r200InitState( r200ContextPtr rmesa )
}
for (i = 0; i < 6; i++)
+ {
if (rmesa->radeon.radeonScreen->kernel_mm)
rmesa->hw.tex[i].emit = tex_emit_cs;
else
rmesa->hw.tex[i].emit = tex_emit;
+ rmesa->hw.tex[i].emit_size += 2;
+ }
if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
@@ -787,9 +790,15 @@ void r200InitState( r200ContextPtr rmesa )
ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
for (i = 0; i < 6; i++)
if (rmesa->radeon.radeonScreen->kernel_mm)
+ {
rmesa->hw.cube[i].emit = cube_emit_cs;
+ rmesa->hw.cube[i].emit_size = 2 + 4*5;
+ }
else
+ {
rmesa->hw.cube[i].emit = cube_emit;
+ rmesa->hw.cube[i].emit_size = 3 + 3*5;
+ }
}
else {
ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
@@ -954,29 +963,46 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa,
R200_EMIT_TCL_POINT_SPRITE_CNTL);
if (rmesa->radeon.radeonScreen->kernel_mm) {
- rmesa->hw.mtl[0].emit = mtl_emit;
- rmesa->hw.mtl[1].emit = mtl_emit;
-
- rmesa->hw.vpi[0].emit = veclinear_emit;
- rmesa->hw.vpi[1].emit = veclinear_emit;
- rmesa->hw.vpp[0].emit = veclinear_emit;
- rmesa->hw.vpp[1].emit = veclinear_emit;
-
- rmesa->hw.grd.emit = scl_emit;
- rmesa->hw.fog.emit = vec_emit;
- rmesa->hw.glt.emit = vec_emit;
- rmesa->hw.eye.emit = vec_emit;
-
- for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
+ rmesa->hw.mtl[0].emit = mtl_emit;
+ rmesa->hw.mtl[0].emit_size += 6; /* VEC + SCL2 */
+ rmesa->hw.mtl[1].emit = mtl_emit;
+ rmesa->hw.mtl[1].emit_size += 6; /* VEC + SCL2 */
+
+ rmesa->hw.vpi[0].emit = veclinear_emit;
+ rmesa->hw.vpi[0].emit_size += 4; /* VECLINEAR */
+ rmesa->hw.vpi[1].emit = veclinear_emit;
+ rmesa->hw.vpi[1].emit_size += 4; /* VECLINEAR */
+ rmesa->hw.vpp[0].emit = veclinear_emit;
+ rmesa->hw.vpp[0].emit_size += 4; /* VECLINEAR */
+ rmesa->hw.vpp[1].emit = veclinear_emit;
+ rmesa->hw.vpp[1].emit_size += 4; /* VECLINEAR */
+
+ rmesa->hw.grd.emit = scl_emit;
+ rmesa->hw.grd.emit_size += 2; /* SCL */
+ rmesa->hw.fog.emit = vec_emit;
+ rmesa->hw.fog.emit_size += 4; /* VEC */
+ rmesa->hw.glt.emit = vec_emit;
+ rmesa->hw.glt.emit_size += 4; /* VEC */
+ rmesa->hw.eye.emit = vec_emit;
+ rmesa->hw.eye.emit_size += 4; /* VEC */
+
+ for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++) {
rmesa->hw.mat[i].emit = vec_emit;
+ rmesa->hw.mat[i].emit_size += 4; /* VEC */
+ }
- for (i = 0; i < 8; i++)
+ for (i = 0; i < 8; i++) {
rmesa->hw.lit[i].emit = lit_emit;
+ rmesa->hw.lit[i].emit_size += 8; /* VEC*2 */
+ }
- for (i = 0; i < 6; i++)
+ for (i = 0; i < 6; i++) {
rmesa->hw.ucp[i].emit = vec_emit;
+ rmesa->hw.ucp[i].emit_size += 4; /* VEC */
+ }
rmesa->hw.ptp.emit = ptp_emit;
+ rmesa->hw.ptp.emit_size += 8; /* VEC*2 */
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c
b/src/mesa/drivers/dri/radeon/radeon_common.c
index 44315ee..b65f5bc 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -951,7 +951,7 @@ static void radeon_print_state_atom_kmm(radeonContextPtr
radeon, struct radeon_s
int dwords = (*state->check) (radeon->glCtx, state);
uint32_t packet0;
- fprintf(stderr, " emit %s %d/%d\n", state->name, dwords,
state->cmd_size);
+ fprintf(stderr, " emit %s %d/%d\n", state->name, dwords,
state->emit_size);
if (RADEON_DEBUG & DEBUG_VERBOSE) {
for (i = 0; i < dwords;) {
--
1.6.3.3
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