On Mon, Nov 07, 2011 at 03:51:50PM +0100, Walter Haidinger wrote:
> cpu0: AMD Phenom(tm) II X6 1100T Processor ("AuthenticAMD" 686-class, 512KB 
> L2 cache) 3.31 GHz
> cpu0: 
> FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,SSE3,CX16,POPCNT
> ...
> bios0: vendor Bochs version "Bochs" date 01/01/2007 
> bios0: Bochs Bochs

They shouldn't be pretending to be AMD, especially if that emulation is 
very incompatible.

> acpicpu0 at acpi0

..but this is fortunate, I can workaround the bug.

> kernel: protection fault trap, code=0
> Stopped at      k1x_init+0x56:  rdmsr
> k1x_init(d0ad7540,d0b8ce58,d059ce20,0,30000002) at k1x_init+0x56
> mainbus_attach(0,d130bfc0,0,d09aafc0,0) at mainbus_attach+0xc1
> config_attach(0,d09aafc0,0,0,d0a1bc40) at config_attach+0x1bb
> config_rootfound(d08cde8c,0,0,d03d8b51,0) at config_rootfound+0x46
> cpu_configure(d0ad7540,1,1000,cff3f000,1) at cpu_configure+0x29
> main(d02004ba,d02004c2,0,0,0) at main+0x3ea
> ddb> 

This wouldn't panic on a real K10 processor, however, it can be avoided here if 
we check acpi before doing the msr read.

Can you try the following?

-Bryan.

Index: amd64/amd64/k1x-pstate.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/k1x-pstate.c,v
retrieving revision 1.2
diff -u -p -u -r1.2 k1x-pstate.c
--- amd64/amd64/k1x-pstate.c    29 May 2011 12:29:28 -0000      1.2
+++ amd64/amd64/k1x-pstate.c    8 Nov 2011 18:18:01 -0000
@@ -75,7 +75,7 @@ struct k1x_cpu_state *k1x_current_state;
 void k1x_transition(struct k1x_cpu_state *, int);
 
 #if NACPICPU > 0
-void k1x_acpi_init(struct k1x_cpu_state *, u_int64_t);
+void k1x_acpi_init(struct k1x_cpu_state *);
 void k1x_acpi_states(struct k1x_cpu_state *, struct acpicpu_pss *, int,
     u_int64_t);
 #endif
@@ -154,14 +154,17 @@ k1x_acpi_states(struct k1x_cpu_state *cs
 }
 
 void
-k1x_acpi_init(struct k1x_cpu_state *cstate, u_int64_t msr)
+k1x_acpi_init(struct k1x_cpu_state *cstate)
 {
        struct acpicpu_pss *pss;
+       u_int64_t msr;
 
        cstate->n_states = acpicpu_fetch_pss(&pss);
        if (cstate->n_states == 0)
                return;
 
+       msr = rdmsr(MSR_K1X_STATUS);
+
        k1x_acpi_states(cstate, pss, cstate->n_states, msr);
 
        return;
@@ -172,12 +175,9 @@ k1x_acpi_init(struct k1x_cpu_state *csta
 void
 k1x_init(struct cpu_info *ci)
 {
-#if NACPICPU > 0
-       u_int64_t msr;
-#endif
-       u_int i;
        struct k1x_cpu_state *cstate;
        struct k1x_state *state;
+       u_int i;
 
        if (setperf_prio > 1)
                return;
@@ -190,7 +190,7 @@ k1x_init(struct cpu_info *ci)
 
 #if NACPICPU > 0
        msr = rdmsr(MSR_K1X_STATUS);
-       k1x_acpi_init(cstate, msr);
+       k1x_acpi_init(cstate);
 #endif
        if (cstate->n_states) {
                printf("%s: %d MHz: speeds:",
Index: i386/i386/k1x-pstate.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/k1x-pstate.c,v
retrieving revision 1.2
diff -u -p -u -r1.2 k1x-pstate.c
--- i386/i386/k1x-pstate.c      29 May 2011 12:29:28 -0000      1.2
+++ i386/i386/k1x-pstate.c      8 Nov 2011 18:18:02 -0000
@@ -75,7 +75,7 @@ struct k1x_cpu_state *k1x_current_state;
 void k1x_transition(struct k1x_cpu_state *, int);
 
 #if NACPICPU > 0
-void k1x_acpi_init(struct k1x_cpu_state *, u_int64_t);
+void k1x_acpi_init(struct k1x_cpu_state *);
 void k1x_acpi_states(struct k1x_cpu_state *, struct acpicpu_pss *, int,
     u_int64_t);
 #endif
@@ -154,14 +154,17 @@ k1x_acpi_states(struct k1x_cpu_state *cs
 }
 
 void
-k1x_acpi_init(struct k1x_cpu_state *cstate, u_int64_t msr)
+k1x_acpi_init(struct k1x_cpu_state *cstate)
 {
        struct acpicpu_pss *pss;
+       u_int64_t msr;
 
        cstate->n_states = acpicpu_fetch_pss(&pss);
        if (cstate->n_states == 0)
                return;
 
+       msr = rdmsr(MSR_K1X_STATUS);
+
        k1x_acpi_states(cstate, pss, cstate->n_states, msr);
 
        return;
@@ -172,12 +175,9 @@ k1x_acpi_init(struct k1x_cpu_state *csta
 void
 k1x_init(struct cpu_info *ci)
 {
-#if NACPICPU > 0
-       u_int64_t msr;
-#endif
-       u_int i;
        struct k1x_cpu_state *cstate;
        struct k1x_state *state;
+       u_int i;
 
        if (setperf_prio > 1)
                return;
@@ -189,8 +189,7 @@ k1x_init(struct cpu_info *ci)
        cstate->n_states = 0;
 
 #if NACPICPU > 0
-       msr = rdmsr(MSR_K1X_STATUS);
-       k1x_acpi_init(cstate, msr);
+       k1x_acpi_init(cstate);
 #endif
        if (cstate->n_states) {
                printf("%s: %d MHz: speeds:",

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