Hi,
I'm currently attempting to use the fll_adjust library function in mspgcc and
feel I must be doing something wrong.
I'm trying to get a 4MHz DCO frequency using a 32.768kHz crystal. The
multiplier here would be around 977 (given 32.768kHz crystal / 8 as ACLK).
I have the following DCO initialisation stages..
DCOCTL = DCO0 | DCO1 | DCO2;
BCSCTL1 = XT2OFF | RSEL2 | DIVA_DIV8; // select 4096 Hz from XT1
BCSCTL2 = 0; // set MCLK=DCO/1, SMCLK=DCO/1, DCO internal
resistor
delay(0xFFFF);
fll_adjust(FLL_MULTIPLIER(4000000, 4096));
Now checking through this with gdb it appears as though fll_adjust is getting
hung up somewhere with a multiplier of 976. It never returns, but it's so
close to the requested frequency.
Is this an issue with fll_adjust? If so, is there a workaround for it, or what
other course of action should I take?
Regards,
Bevan Weiss
_________________________________________________________________
Discover the new Windows Vista
http://search.msn.com/results.aspx?q=windows+vista&mkt=en-US&form=QBRE
