Chris Liechti wrote:
Bevan Weiss schrieb:
fll_adjust(FLL_MULTIPLIER(4000000, 4096));
Now checking through this with gdb it appears as though fll_adjust is
getting hung up somewhere with a multiplier of 976. It never returns,
but it's so close to the requested frequency.
Is this an issue with fll_adjust?
it works fine for me at least for 1.5 and 3.0 MHz
> If so, is there a workaround for it,
or what other course of action should I take?
are you sure your device works properly with 4MHz? VCC high enough?
4... 5 MHz is the maximum DCO frequency for F1xx devices with the
internal resistor (at room temperature and 3 volts i have always seen a
minimum of >4.5MHz)
but maybe are the DCO ranges not overlapping?
I'm currently using around 4.9MHz just hardcoded with the DCO settings,
however wanted something better across voltage, temperature and
process. It's all being powered from 3.3V so that shouldn't be an
issue. It's a MSP430F149 device, however it operates fine with the
4.9MHz DCO clock, so don't see that as being the problem. I had thought
it might be the ACLK not settling, but I'm running the watchdog interval
timer off that (for 1 sec RTC tick) and that seems fine.
if you have a parallel port JTAG you can check the DCO ranges with
msp430-dco --measure
chris
I've got a parallel port JTAG here at home, so will take that to work
tomorrow to check it out.
Just seems like a really strange problem, how long should it take to
perform its first lock? I've waited for like 5 minutes (which would be
an unacceptable start up delay) without any resolution to the lock
situation.
