On 06/04/11 17:58, JMGross wrote: >> Not all "RISC" architectures have all of the above, but simply having >> a small instruction count just isn't good enough IMO. > > On the contrary, that's the only criteria. A small instruction count of > fast instructions compared to a high instruciton count of complex > and slow instructions.
This is a common misconception. A RISC architecture is /not/ one with a reduced /set/ of instructions, it one with a set of reduced /instructions/. The defining issue for RISC is that the instructions are not logically divisible. Since the msp430 makes so much use of RMW instructions, which are inherently divisible into three distinct operations, it is not a RISC processor. Very few, if any, cpu designs are "pure RISC". Most have some sort of extra instructions for a few special cases to optimise speed, code size, or hardware - typical examples being instructions to save or restore multiple registers. There are also many features that can be considered "typical RISC features", and many features that can be considered "typical CISC features". From that viewpoint, RISC vs. CISC is a scale, with "pure RISC" at one end, and "pure CISC" at the other. On that scale, the msp430 is pretty much middle of the line. ------------------------------------------------------------------------------ Xperia(TM) PLAY It's a major breakthrough. An authentic gaming smartphone on the nation's most reliable network. And it wants your games. http://p.sf.net/sfu/verizon-sfdev _______________________________________________ Mspgcc-users mailing list Mspgcc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/mspgcc-users
