On Wed, 17 Mar 1999 [EMAIL PROTECTED] wrote:
> My project with MegaRAM uses a double-bank of mapped
> registers (16 bytes select ever 8kb block).
And how do you think you'll make the registers? Will you use the even
addresses to select LSB and odd addresses to select MSB?
> Reference for Mapped circuits are available on Elektor
> Electronics Magazine. Principles of mapper are publis-
> hed by brazilian Elektor on july'1986. The article
> name is "Eprom Expansions".
Elektor? That magazine is made for begineers. I prefer "Circuit Cellar",
by Steve Ciarcia, available in http://www.circuitcellar.com/
If you don't remember, Steve Ciarcia is the writter of the book called
"Construct your own Microcomputer using Z80", McGrawHill.
> >>>> -EXACTLY what memory ranges do these blocks occupy?
> >>> There are blocks in the area 4000h-5FFFh, 6000h-7FFFh, 8000h-9FFFh and
> >>> A000-BFFFh.
>
> Graphic block diagram is:
>
> MEGARAM SLOT MEGARAM BLOCKS
>
> +-------------+ +----> +-------------+
> | 0000h-3FFFh | | | 4000h-5FFFh | Block 0
> +-------------+ ------+ +-------------+
> | 4000h-7FFFh | | 6000h-7FFFh | Block 1
> +-------------+ +-------------+
> | 8000h-BFFFh | | 8000h-9FFFh | Block 2
> +-------------+ ------+ +-------------+
> | C000h-FFFFh | | | A000h-BFFFh | Block 3
> +-------------+ +----> +-------------+
Since that the mirror effect was known, this diagram isn't absolutely the
truth.
> >This implies that, when you select a block
> >over page 0, it will be selected on page 2, too. The same is valid for
> >page 3, that acts on page 1, too.
>
> The most mysteriuos MegaRAM's feature is the mirror :)
> MSB of address bus (A15) is ignored by MegaRAM!
Yes, the creator of Megaram (Ademir Carchano) told me that he ignored A15
to make the hardware much more simple, and to fit in a standard cartridge
box.
> >So, you can use Megaram on page 0 and page 3, but when you're in "block
> >select mode"
>
> IN A, (8Eh)
No, "block select mode" is accessed by a OUT (8Eh),A
> >and do a LD A,04h / LD (0000h),A the block 4 is selected for
> >the area 0000h-1FFFh and also for 8000h-9FFFh.
>
> If Slot (and sub-slot) Register are enable for same
> cartridge. If not, you can select and read/write on
> this 1st address, but not read/write on mirrored.
Of course! Everything that I was talking about is valid only when all
pages are selected over the slot where Megaram is connected.
> You can use 4 MegaRAM for every 16kb on same computer,
> 1st MegaRAM on 0-3FFFh, 2nd on 4000h-7FFFh, 3th on
> 8000h-BFFFh, and 4th on C000h-FFFFh. The (8Eh) port
> sets "block select/read mode" when OUT, or "write/read
> mode" when IN.
Right.
> The same mechanic is used for "MegaRAM Disk" cartridge
> on (8Fh) port, for enable internal DiskROM for
> RAMDISK emulation.
Yes, the ports affect all Megarams connected to the system.
> > The opposite is also valid,
> >when you do a LD A,04h / LD (8000h),A the block 4 is selected for the area
> >8000h-9FFFh and also for 0000h-1FFFh. That's exactly what you said about
> >many Megaroms (the most part of Konami ones).
>
> Mirror or "shadow" is the best name for ?
For Megaram, mirror is best. But if Konami SCC Megarom works exactly like
Alwin described, then shadow is best for Konami SCC Megarom.
> >> Second, if write-enable or block-switch state is undefined after a
> >> reset,
>
> No. The mode is undefined when computer startup,
> after reset none changes are made on this register.
That's what I explained in the next related e-mail!
> >> it could ofcourse be in write-enable state at the time of
> >> reset, and behaving as normal RAM then, be detected as such (be it
> >> at 4000-BFFFh only).
>
> Yes, will be detected as normal RAM. But how much RAM
> is found depends of registers value.
That can happen when you do a reset while Megaram is in "write enable
mode". But I don't know how much memory will be detected as normal RAM.
Does the BIOS verify if the mirror effect happens?
> >But that's a good question! The computer could think that it's a normal
> >RAM if the state is "write enable mode" while the slots are being scanned.
> >I don't know how to answer your question, I guess that the start-up state
> >should be "block select mode", but I'm not sure.
>
> No changes are made when startup sequence begins.
> MegaRAM are "RESET-insensitive". See technical informa
> tion and electrical diagram on CPU MSX Magazine nr 35.
Don't trust in that magazine! I'll analyse the contents of those
schematics to see if there aren't any bugs.
> > Simple and good method: select (in descending order) each possible
> > block, write its number in it in at some test address, and then
> > (starting with block 0) check up until which block the block number
> > matches what you find at the test address when selecting each block.
> (...)
> >I think that this method has a fault
>
> Many faults for a test program...
Then show us which faults you are seeing!
> >> If it exists, you can change the MegaRAM-disk from (EP)ROM state into
> >> RAM state and vice versa (using both I/O ports), and detect that ->
> >> MegaRAM-disk.
> >Yes, but usually there's no need for that.
>
> ROM state is ON or OFF.
> No ROM are mapped on MegaRAM Disk.
Sure! That's another small detail that I had forgotten to show.
> > The FDC used in European MSX machines is either a TMS 1793 or 2793(...)
> > All other European MSX's, and separate disk interfaces (Philips,
> > Toshiba, Sony etc.) that I've seen, use the TMS 2793.
>
> I shop 4 ICs WD2793BL... but no have schematics for!!!
A friend of mine sended to me a copy of the port based disk interface, and
I saw that it really uses WD2793 FDC. So, now I answered Alwin's question.
> >So do I. Recently, Alex Wulms explained to me how these FDCs work, and
> >they work like the port based FDC. The main difference is that addresses
> >7FF8h-7FFBh is mapped to ports D0h-D4h. There are other minor differences,
> >but they are not important.
>
> More tech info for help me on FDC concepts ?
FDC concepts?
port D0h or address 7FF8h - read=status write=command
port D1h or address 7FF9h - current track number
port D2h or address 7FFAh - sector number
port D3h or address 7FFBh - data I/O
port D4h or address 7FFCh - drive select, side select and motor on/off
For Turbo-R FDC, things are completely different. The commands and the
status are composed by many bytes, that must be read or written
sequentially to address 7FF4h, when address 7FF2h indicates that the FDC
is ready to receive or send the next byte of the command or status. 7FF5h
is the data I/O. 7FF3h is a port where we should write 20h or 30h for
certain operations, but I don't know the purpose. Does anybody know?
> >I had talked to Alex Wulms and he had said it has these datasheets, but
> >that's only in paper. So, I couldn't get it. If you know some cheap way of
> >sending information from paper to other countries, please contact me.
>
> Only few copies are "sactisfaction" for me.
But international snail mail will be too much expensive.
> >Ok, that's a good idea. The main idea is to get the knowledge used to make
> >the disk copier and create an entire new operating system, much more
> >efficient.
>
> Marco, a name of project (SODA) is definitive ?
No, it can be changes when someone suggest a better name for it.
> > But one of the difficulties is to understand how the all kinds
> >of MSX hardware work, because the variability is really big
>
> I think 1st priority detect all kinds of RAM.
That's the easy part. But we don't know how IDE, xxxxSCSI, MoonSound and
GFX9000 work. Are there technical documentation available for download?
> >> You seem to know what you're talking about here, and I myself don't
> >> have a MegaRAM.
>
> Wait for G-RAM(TM) (MegaRAM with 16-bit registers)
> padronization. Will alocate 512Mbytes RAM/each slot.
Is the "G" from "G-RAM" a abbreviation of "gambiarra"? :-)
Greetings from Brazil!
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Marco Antonio Simon Dal Poz http://www.lsi.usp.br/~mdalpoz
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