Marco Antonio Simon dal Poz <[EMAIL PROTECTED]> wrote:
>> My project with MegaRAM uses a double-bank of mapped
>> registers (16 bytes select ever 8kb block).
>And how do you think you'll make the registers? Will you use the even
>addresses to select LSB and odd addresses to select MSB?
The great idea is more or less this:
OUT (8Fh), A disable G-RAM (or enable ROM)
OUT (8Eh), A enable LSB exp. address for bank switch
OUT (8Ch), A enable MSB exp. address for bank switch
IN A, (8Ch~8Fh) disable write protection and bank
switching, but not modify register
state of "8Fh".
>> Reference for Mapped circuits are available on Elektor
>> Electronics Magazine.
>Elektor? That magazine is made for begineers.
"Beginner" is my secound name.
"Ambitious" is my third name :))))
>I prefer "Circuit Cellar",by Steve Ciarcia
I collect copies of circuit cellar on BYTE small systems
journal (USA/1979~1988). Thanks for remind !
>If you don't remember, Steve Ciarcia is the writter of the book called
>"Construct your own Microcomputer using Z80", McGrawHill.
I have a copy, too. :))))
And plan to make a PCB for this schemes.
>>>>>> -EXACTLY what memory ranges do these blocks occupy?
>>>>> There are blocks in the area 4000h-5FFFh, 6000h-7FFFh, 8000h-9FFFh and
>>>>> A000-BFFFh.
>>Graphic block diagram is:
>Since that the mirror effect was known, this diagram isn't absolutely
>the truth.
Ok, I made new correct ASCII block diagram.
>>The most mysteriuos MegaRAM's feature is the mirror :)
>>MSB of address bus (A15) is ignored by MegaRAM!
>Yes, the creator of Megaram (Ademir Carchano) told me that he
>ignored A15 to make the hardware much more simple,
>and to fit in a standard cartridge box.
Jeannie...(ops!) Ademir... is a genious!
>>>So, you can use Megaram on page 0 and page 3, but when you're in "block
>>>select mode"
>No, "block select mode" is accessed by a OUT (8Eh),A
I made a mistake when read EAB's Programmers Guide :(((
You're right.
>Everything that I was talking about is valid only when all
>pages are selected over the slot where Megaram is connected.
(correct) Diagram for illustrate this resource:
MEGARAM SLOT MEGARAM BLOCKS
(enabled)
+-------------+ -----------> +-------------+
| 0000h-3FFFh | | 0000h-1FFFh | Block 0
+-------------+ +-------------+
| 4000h-7FFFh | | 2000h-3FFFh | Block 1
+-------------+ +-------------+
| 8000h-BFFFh | | 4000h-5FFFh | Block 2
+-------------+ +-------------+
| C000h-FFFFh | | 6000h-7FFFh | Block 3
+-------------+ ------+ +-------------+
| | 8000h-9FFFh | Block 0'
| +-------------+
| | A000h-BFFFh | Block 1'
| +-------------+
| | C000h-DFFFh | Block 2'
| +-------------+
+----> | E000h-FFFFh | Block 3'
+-------------+
(Blocks marked with "'" are mirrors of same block)
>That can happen when you do a reset while Megaram is in "write enable
>mode". But I don't know how much memory will be detected as normal RAM.
>Does the BIOS verify if the mirror effect happens?
Ok, the CHKRAM started on E000h, and decrease counter
when search RAM... don't know how more is effective.
>> MegaRAM are "RESET-insensitive". See technical informa
>> tion and electrical diagram on CPU MSX Magazine nr 35.
>Don't trust in that magazine! I'll analyse the contents of those
>schematics to see if there aren't any bugs.
The scheme do not use /RESET signal for clear MegaRAM
registers. I'm based on CPU MSX scheme.
>>> Simple and good method: select (in descending order) each possible
>>> block, write its number in it in at some test address, and then
>>> (starting with block 0) check up until which block the block number
>>> matches what you find at the test address when selecting each block.
>> Many faults for a test program...
>Then show us which faults you are seeing!
Checking for multiple-redundance nodes, and check for
individual address bus lines minimize time on search
size of available RAM.
Think how much time CPU need for measure the entire
RAM connected at slots. This way is unreasonable!
>> I shop 4 ICs WD2793BL... but no have schematics for!!!
>A friend of mine sended to me a copy of the port based disk interface, and
>I saw that it really uses WD2793 FDC.
The same friend send to me the copy of diagrams of this
interface, too. But I don't know to make adjust.
>FDC concepts?
Thanks for explain.
>>> But one of the difficulties is to understand how the all kinds
>>>of MSX hardware work, because the variability is really big
>>I think 1st priority detect all kinds of RAM.
>That's the easy part.
Not so easy. Several kinds of RAM is available:
Cartridge 64kb RAM standart, MegaRAM, MegaRAM-Disk,
Ext. Mapper, (new)G-RAM, 8/16/32kb SRAM modules...
Found size of RAM isn't all of test...
I need mark the Wait cicles required for read/write on
any kinds of RAM available on system.
I collect tricks for detect this kinds.
>But we don't know how IDE, xxxxSCSI, MoonSound and
>GFX9000 work.
>Are there technical documentation available for download?
SCC, SCC+, SCC2, EPP port and IR-interface padronization
are welcome too.
>> Wait for G-RAM(TM) (MegaRAM with 16-bit registers)
>> padronization. Will alocate 512Mbytes RAM/each slot.
>Is the "G" from "G-RAM" a abbreviation of "gambiarra"? :-)
<.br>
"G" vem de GODZILLA, ficou bacana ?
Mas nao espalha meu, senao posso me dar mal ! :))))
</.br>
MARUJO.
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