> My current problem with NLMSX:
>
> I am looking for more information about bit 0 of status register#1. (FH
bit)
This bit is set when the VDP arrives at the line specified in VDP register
19.
It is reset when it is read.
If the bit IE1 in register 0 is set then an interrupt will be generated if
the FH bit is set. The interrupt will keep being generated until the FH bit
becomes reset. You must see it as a copy from the FH bit on the
interrupt-input of the Z80. So:
1. the interrupt routine starts with a DI. If the interrupts are enabled
before the interrupt-routine RETurns (so not using the EI:RET combination at
the end) a new interrupt will be generated resulting in an infinite loop and
finally a stack overflow.
2. Unless status-register 1 is being read during the DI (interrupts
disabled -> Z80 doesn't acknowledge incoming interrupts).
If the IE1-bit is reset, then no interrupt will be generated, however you
can still poll the FH bit (used a lot, probably in SRM too).
> reg#1, bit 5, Horizontal scanning line, Interrupt Enable 0
Wrong, not "Horizontal scanning line". With this bit you can en- and disable
the normal interrupt (every 1/50th or 1/60th second when the VDP arrives at
line 212).
So it's got nothing (well almost nothing) to do with this issue.
Well, got it now??? If you get the basics then it's quite simple... Maybe
you should make a hardcopy (on paper) of Stefan Boer's VDP cursus or the
official v9938 (or 58) application manual... I think you are using some docs
not covering all (or covering things incorrectly).
If you need any more help on the VDP, feel free to mail me.
~Grauw
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