All, My preliminary check this afternoon shows me that there is a timing issue at U15, the 74ls02. Using my logic analyzer and monitoring the inputs and the output (which clocks the flip flop) I see a big timing difference between SEL_SECOND and WR. What this means is that the output of the gate never goes high.
I am going to start a new post to document and deal with the troubleshooting of this problem. Thanks, Thomas -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
