Guy’s just took a look at the schematic. Not crazy about how the write signals (WR* etc.) are driven by open collectors + pull-ups, if I were to do it again I would use one input of a 74LS08 (the other tied high) for S100 non inverted inputs – less slew. However it should not be a problem because SEL_SECOND and DO0 are well settled before WR* goes low.
If I was going to fool around with anything I would try dropping R30 /R31 to lower (or higher) values. Would have liked to use higher powered 7407 for U17 E & F, but unfortunately U17 inputs S100 lines A0, A1, this will load the bus more that I would like. I always try and have 74LS on S100 inputs – at least in my 21 Card system. I have to stress all these CF cards don’t behave the same way. The Kingston 4GB ones I use never have a problem switching between drives. Is that what you are using. John From: [email protected] [mailto:[email protected]] On Behalf Of yoda Sent: Sunday, June 8, 2014 7:09 PM To: [email protected] Subject: Re: [N8VEM-S100:4050] Re: Run of Dual CF-Card/Hard Disk IDE S-100 Boards It really has nothing to do with the cards as the select is driven by a flip-flop - I see the same thing on my board but have not set down yet to debug what is going on but Thomas is right there is some timing problem is going on as DO0 is clocked into the flip-flop via SEL_SECOND* and WR* being combined - there is a mis-timing of the signals as that really is the only thing that could cause this - guess others have been lucky or have not tried to use the second CF card. Dave On Sunday, June 8, 2014 7:42:16 PM UTC-5, Tom Lafleur wrote: fyi... One of the issues John has pointed out in the past, is that the current software/hardware is VERY SELECTIVE on what brand and model of cards that work with this board... It maybe necessary at some point to redo his code based on the Z80 Zeta code or other ?, that handles a large number of cards... I'm sure its a timing issues... but it may need someone to look at it in detail... On Sun, Jun 8, 2014 at 7:43 PM, Thomas Owen <[email protected] <javascript:> > wrote: All, My preliminary check this afternoon shows me that there is a timing issue at U15, the 74ls02. Using my logic analyzer and monitoring the inputs and the output (which clocks the flip flop) I see a big timing difference between SEL_SECOND and WR. What this means is that the output of the gate never goes high. I am going to start a new post to document and deal with the troubleshooting of this problem. Thanks, Thomas -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected] <javascript:> . For more options, visit https://groups.google.com/d/optout. -- ~~ _/) ~~~~ _/) ~~~~ _/) ~~~~ _/) ~~ Tom Lafleur (858) 759-9692 -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
