After setting up the logic analyzer the following are the waveforms observed:
Channel A0: U15 pin 1, Out Channel A1: U15 pin 2, SEL_SECOND Channel A2: U15 pin 3, WR Channel A3: U16 pin 2 , bDO0 The first images shows the following command entered at the console: QO34, 00 <https://lh5.googleusercontent.com/-5Dh8m9FoVBA/U5XZTvtJ0YI/AAAAAAAABXg/sQzmz1hHXTg/s1600/QO34_00.jpg> The next image is the result of the command: QO34,1 <https://lh3.googleusercontent.com/-4HPQBPDAa2U/U5XZs2Sel2I/AAAAAAAABXs/bKJCne1uOf8/s1600/QO34_01.jpg> So we can see that the proper signals exist at the Drive Select 7474 flip flop, yet the drive select leds never change. Anyone see anything out of the ordinary? More tests this afternoon. Thanks <https://lh5.googleusercontent.com/-5Dh8m9FoVBA/U5XZTvtJ0YI/AAAAAAAABXg/sQzmz1hHXTg/s1600/QO34_00.jpg> On Sunday, June 8, 2014 7:58:45 PM UTC-4, Thomas Owen wrote: <https://lh5.googleusercontent.com/-5Dh8m9FoVBA/U5XZTvtJ0YI/AAAAAAAABXg/sQzmz1hHXTg/s1600/QO34_00.jpg> > All, > I had posted this to the thread dealing with ordering this card, but > decided to post a new topic dealing with the problem I have had with final > checkout of the board. > > > During assembly the board passed all the 'in progress' checks. The final > steps were to output to different ports: > > > I have output the following and everything passes: > > QO33,80 ; Configures ports A, B and C as output ports > QO32,2B ; Selects right hand pair of digits > QO30,01; display 01on right digit pair and work through each bit - all ok > > QO32,2c; Selects middle pair of digits > QO30,01; Should display 01 on middle digit pair, work through each bit - > all ok > > QO32,2d; Selects left hand pair of digits > QO31,01; Should display 01 on left digit pair, work through each bit - all > ok > > All displays are correct. > > Now the final step is the Drive Select and that is where I am having > trouble: > > Board always comes up with 'Drive A' selected > > Now, QO34,0; no change > > Reset, start again: > > QO34,1; no change > > I can never select drive B. > > Several generous members (thank you David Fry) have made suggestions, and > here is where I now stand: > > My preliminary check this afternoon shows me that there is a timing issue > at U15, the 74ls02. Using my logic analyzer and monitoring the inputs and > the output (which clocks the drive select flip flop) I see a big timing > difference between SEL_SECOND and WR. > > What this means is that the output of the gate never goes high allowing > the bit change to effect drive change/selection. > > I am going to get some screen shots from the analyzer tomorrow, and if > anyone has any suggestions I would greatly appreciate it. > > Thanks, > Thomas > > -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
