Dave, have a quick look at gates U6C, U6D & U11F U7 will not be active for port address 034H Thomas, out of interest what CPU card are you using ? regards David Fry
On Monday, June 9, 2014 5:45:01 PM UTC+1, yoda wrote: > John > > I will say it again - the type of CF card can have no effect on this > circuit. Why is DO0 run through the 7407 anyways - it is already buffered > at the 244 U7? I think there is so much delay introduced in the circuit > that DO0 is never really stable when it is clocked into the 7474. I think > it is a race situation and you are lucky if it can ever be deterministic. > I guess one thing that might be tried is to eliminate the 7407 by bending > out pin 2 of U16 and connecting it to pin 18 of U7? Don't know if that > is going to help or not. Thomas can you put logic analyzer on pin 2 and 3 > of U16 so we can see the timing relation between the 2 signals - that will > tell what is being clocked in. > > Dave > > On Monday, June 9, 2014 11:19:35 AM UTC-5, monahanz wrote: >> >> Sorry I meant actual CF card itself, Kingston, etc.. >> >> John >> >> >> >> >> >> *From:* [email protected] [mailto:[email protected]] *On >> Behalf Of *Thomas Owen >> *Sent:* Monday, June 9, 2014 9:16 AM >> *To:* [email protected] >> *Subject:* [N8VEM-S100:4063] Re: CF IDE card checkout and final assembly >> problem >> >> >> >> John, >> >> It is the newest batch I believe, '02a'. >> >> Thanks >> >> On Sunday, June 8, 2014 7:58:45 PM UTC-4, Thomas Owen wrote: >> >> All, >> I had posted this to the thread dealing with ordering this card, but >> decided to post a new topic dealing with the problem I have had with final >> checkout of the board. >> >> During assembly the board passed all the 'in progress' checks. The final >> steps were to output to different ports: >> >> >> I have output the following and everything passes: >> >> QO33,80 ; Configures ports A, B and C as output ports >> QO32,2B ; Selects right hand pair of digits >> QO30,01; display 01on right digit pair and work through each bit - all ok >> >> QO32,2c; Selects middle pair of digits >> QO30,01; Should display 01 on middle digit pair, work through each bit - >> all ok >> >> QO32,2d; Selects left hand pair of digits >> QO31,01; Should display 01 on left digit pair, work through each bit - >> all ok >> >> All displays are correct. >> >> Now the final step is the Drive Select and that is where I am having >> trouble: >> >> Board always comes up with 'Drive A' selected >> >> Now, QO34,0; no change >> >> Reset, start again: >> >> QO34,1; no change >> >> I can never select drive B. >> >> Several generous members (thank you David Fry) have made suggestions, and >> here is where I now stand: >> >> My preliminary check this afternoon shows me that there is a timing issue >> at U15, the 74ls02. Using my logic analyzer and monitoring the inputs and >> the output (which clocks the drive select flip flop) I see a big timing >> difference between SEL_SECOND and WR. >> >> What this means is that the output of the gate never goes high allowing >> the bit change to effect drive change/selection. >> >> I am going to get some screen shots from the analyzer tomorrow, and if >> anyone has any suggestions I would greatly appreciate it. >> >> Thanks, >> Thomas >> >> -- >> You received this message because you are subscribed to the Google Groups >> "N8VEM-S100" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to [email protected]. >> For more options, visit https://groups.google.com/d/optout. >> > -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
